PCA9560D,112 NXP Semiconductors, PCA9560D,112 Datasheet - Page 8

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PCA9560D,112

Manufacturer Part Number
PCA9560D,112
Description
IC I2C EEPROM DIP SWITCH 20-SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9560D,112

Package / Case
20-SOIC (7.5mm Width)
Applications
Networking
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3401-5
935270331112
PCA9560D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9560D,112
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
2004 May 19
Dual 5-bit multiplexed 1-bit latched
I
2
C EEPROM DIP switch
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START condition
S
Figure 8. Acknowledgement on the I
1
2
8
not acknowledge
acknowledge
8
2
C-bus
9
clock pulse for
acknowledgement
PCA9560
Product data sheet
SW00368

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