W83977G-A Nuvoton Technology Corporation of America, W83977G-A Datasheet
W83977G-A
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... WINBOND I/O W83977F-A/W83977G-A W83977AF-A/W83977AG-A & ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A W83977F/ AF Data Sheet Revision History PAGES DATES 1 n.a. 01/20/97 2 2,3,6,8,9,10, 01/27/97 122,126,128- 132,134,138,168 3 117-125,127 01/30/97 4 9,10,120-122 02/13/97 5 127,135,136,169 03/03/97 6 VIII,IX,166-169 05/24/97 7 P118 7/15/97 8 53,54,58,61,62, 11/17/97 63,65,124,125 9 1,3,11,52,91,105, 03/10/98 109,110,111,113, 114,115,119,124, 130,131,148 10 n.a. 05/02/06 VERSION VERSION ON WEB 0.50 First publication 0 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Table of Contents- 1. GENERAL DESCRIPTION ................................................................................................................ 1 2. FEATURES ........................................................................................................................................ 2 3. PIN CONFIGURATION...................................................................................................................... 5 4. PIN DESCRIPTION ........................................................................................................................... 6 4.1 Host Interface.......................................................................................................................... 6 4.2 Advanced Power Management............................................................................................... 8 4.3 Serial Port Interface ................................................................................................................ 9 4.4 Infrared Interface................................................................................................................... 10 4.5 Multi-Mode Parallel Port........................................................................................................ 11 4.6 FDC Interface........................................................................................................................ 15 4.7 KBC Interface........................................................................................................................ 16 4.8 RTC Interface ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6.2.6 Interrupt Status Register (ISR) (Read only) ............................................................................45 6.2.7 Interrupt Control Register (ICR) (Read/Write).........................................................................46 6.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write).......................................................46 6.2.9 User-defined Register (UDR) (Read/Write) ............................................................................47 7. INFRARED (IR) PORT..................................................................................................................... 48 7.1 IR Register Description ......................................................................................................... 48 7.2 Set0-Legacy/Advanced IR Control and Status Registers..................................................... 49 7.2.1 Set0 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.7.6 Set5.Reg6 Receiver Frame Length FIFO (RFLFL/RFLFH) or Lost Frame Number (LST_NU) .............................................................................................................................................69 7.8 Set6 - IR Physical Layer Control Registers .......................................................................... 70 7.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)...........................................................70 7.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width..............................................................71 7.8.3 Set6.Reg2 - SIR Pulse Width .................................................................................................72 7.8.4 Set6.Reg3 - Set Select Register.............................................................................................72 7 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.4 Extension FDD Mode (EXTFDD) .......................................................................................... 95 8.5 Extension 2FDD Mode (EXT2FDD) ...................................................................................... 95 9. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL ............................................................... 96 9.1 REGISTER ADDRESS MAP................................................................................................. 96 9.2 Update Cycle......................................................................................................................... 98 9.3 REGISTERS ......................................................................................................................... 99 9.3.1 Register 0Ah...........................................................................................................................99 9.3.2 Register 0Bh (Read/Write) ...................................................................................................100 9.3.3 Register 0Ch (Read only) .....................................................................................................101 9 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 12.2.1 Extended Function Registers................................................................................................118 12.2.2 Extended Functions Enable Registers (EFERs) ...................................................................119 12.2.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs) .119 13. CONFIGURATION REGISTER ..................................................................................................... 120 13.1 Chip (Global) Control Register............................................................................................ 120 13.2 Logical Device 0 (FDC) ....................................................................................................... 125 13.3 Logical Device 1 (Parallel Port)........................................................................................... 128 13.4 Logical Device 2 (UART A)¢ ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.4.1 Write Cycle Timing ...............................................................................................................165 15.4.2 Read Cycle Timing ...............................................................................................................165 15.4.3 Send Data to K/B..................................................................................................................165 15.4.4 Receive Data from K/B .........................................................................................................166 15.4.5 Input Clock ...........................................................................................................................166 15.4.6 Send Data to Mouse.............................................................................................................166 15.4.7 Receive Data from Mouse ....................................................................................................166 15.5 GPIO Write Timing Diagram ............................................................................................... 167 15 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 1. GENERAL DESCRIPTION This data sheet covers two products: W83977F/G, and W83977AF/AG whose pin assignment, and most of the functions are the same. W83977AF/ advanced version of W83977F/G featuring the FIR function. W83977F/G, W83977AF/AG are evolving products from Winbond’s most popular I/O chip W83877F -- - which integrates the disk drive adapter, serial port (UART), IrDA 1 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 2. FEATURES General Plug & Play 1.0A Compliant Support 13 IRQs, 4 DMA channels, full 16-bit addresses decoding Capable of ISA Bus IRQ Sharing Compliant with Microsoft PC97 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings 24 or 14.318 Mhz clock input ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Infrared Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Support IrDA version 1.1 MIR (1.152M bps) and FIR (4M bps) protocol [W83977AF/AG only] ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Real Time Clock 27 bytes of clock, On-Now, and control/status register (14 bytes in Bank 0 and 13 bytes in Bank 2); 242 bytes of general purpose RAM BCD or Binary representation of time, calendar, and alarm registers Counts seconds, minutes, hours, days of week, days of month, month, year, and century 12-hour/ 24-hour clock with AM/PM in 12-hour mode Daylight saving time option ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 3. PIN CONFIGURATION 103 IRQ14/GP14 104 IRQ15/GP15 105 IOR 106 IOW AEN 107 IOCHRDY 108 109 D0 D1 110 111 D2 112 D3 113 D4 D5 114 115 VCC 116 D6 117 D7 118 MR 119 DACK0/GP16 120 VSS 121 DRQ0/GP17 122 DACK1 123 DRQ1 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 4. PIN DESCRIPTION Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. I/O6t - TTL level bi-directional pin with 6 mA source-sink capability I/O8t - TTL level bi-directional pin with 8 mA source-sink capability I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Host Interface, continued. SYMBOL PIN I/O 119 IN ts DACK0 GP16 (WDTO) I/O 12t P15 I/O 12t RTSC OUT 12t DRQ0 121 OUT 12t GP17 I/O 12t (PLEDO) P14 I/O 12t DTRC OUT 12t 122 IN ts DACK1 DRQ1 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Host Interface, continued. SYMBOL PIN I/O IRQ14 103 OUT 12t GP14 I/O 12t GPACS ( ) PLED OUT 12t IRSL1 OUT 12t IRQ15 104 OUT 12t GP15 I/O 12t GPAWE ( ) WDT OUT 12t IRSL2 OUT 12t CLKIN 4.2 Advanced Power Management ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Advanced Power Management, continued. SYMBOL PIN I/O GP23 (P15) I/O 12t DCDC IN t 4.3 Serial Port Interface SYMBOL PIN I CTSA 48 CTSB DSRA 49 DSRB 43 I/O 8t RTSA HEFRAS 50 I/O 8t RTSB nPENPLL 44 I/O 8t DTRA PNPCSV 51 I/O 8t DTRB ENCPNP 45 SINA SINB FUNCTION CR2B bit7, 6=01: General purpose I/O port 2, bit 3 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Serial Port Interface, continued. SYMBOL PIN I/O 46 I/O 8t SOUTA PENKRC SOUTB 53 I DCDA t DCDB RIA t 66 RIB 4.4 Infrared Interface SYMBOL PIN I/O IRRX (SINC IRTX 38 OUT 12t (SOUTC) IRRXH 39 I/O 12t IRSL0 OUT 12t GP25 (GA20) ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 4.5 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL PIN I/O SLCT BUSY FUNCTION PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Multi-Mode Parallel Port, continued. SYMBOL PIN I ACK ERR SLIN INIT FUNCTION ACK PRINTER MODE: An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Multi-Mode Parallel Port, continued. SYMBOL PIN I AFD STB - - PD0 31 I/O 24t PD1 30 I/O 24t PD2 29 I/O 24t FUNCTION AFD PRINTER MODE: An active low output from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to description of the parallel port for definition of this pin in ECP and EPP mode ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Multi-Mode Parallel Port, continued. SYMBOL PIN I/O PD3 28 I/O 24t PD4 27 I/O 24t PD5 26 I/O 24t - - PD6 24 I/O 24t - OD 24 PD7 23 I/O 24t - OD 24 FUNCTION PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to description of the parallel port for definition of this pin in ECP and EPP mode ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 4.6 FDC Interface SYMBOL PIN I/O DRVDEN0 DRVDEN1 GP10 (IRQIN1) P12 DSRC HEAD STEP DIR MOB DSA DSB MOA DSKCHG RDATA TRAK0 INDEX FUNCTION Drive Density Select bit 0. Drive Density Select bit 1. Alternate Function 1: General purpose I/O port 1, bit 0. It can be configured as an interrupt channel ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 4.7 KBC Interface SYMBOL PIN I/O KDATA 59 I/OD 16u MDATA 60 I/OD 16u KCLK 67 I/OD 16u MCLK 68 I/OD 16u GA20 56 OUT 12t GP11 I/O 12t (IRQIN2) KBRST 57 OUT 12t GP12 I/O 12t (WDTO, IRRX) KBLOCK 58 IN 16tu GP13 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5. FDC FUNCTIONAL DESCRIPTION 5.1 W83977F/G and W83977AF/AG FDC The floppy disk controller of the W83977F/G, W83977AF/AG integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5.1.6 FDC Core The W83977F/G, W83977AF/AG FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (2) Read Deleted Data PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS DS1 DS0 - REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (3) Read A Track PHASE R/W D7 Command W 0 MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (4) Read ID PHASE R/W D7 Command W 0 MFM Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (5) Verify PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (6) Version PHASE R/W D7 Command W 0 Result HDS DS1 DS0 - REMARKS 0 Command codes Sector ID information prior ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (7) Write Data PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (8) Write Deleted Data PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (9) Format A Track PHASE R/W D7 Command W 0 MFM ---------------------- N ------------------------ W --------------------- SC ----------------------- W --------------------- GPL --------------------- W ---------------------- D ------------------------ ---------------------- C ------------------------ Execution W for Each W ---------------------- H ------------------------ Sector W ---------------------- R ------------------------ Repeat: W ---------------------- N ------------------------ Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command Execution (11) Sense Interrupt Status PHASE R Command Result ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (13) Seek PHASE R/W D7 Command -------------------- NCN ----------------------- Execution R (14) Configure PHASE R/W D7 Command --------------------PRETRK ----------------------- | Execution (15) Relative Seek PHASE R/W D7 Command W 1 DIR -------------------- RCN ---------------------------- | (16) Dumpreg PHASE R/W D7 Command W 0 Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- R ----------------------- PCN-Drive 3 ------------------- R --------SRT ------------------ | --------- HUT -------- ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (17) Perpendicular Mode PHASE R/W D7 Command (18) Lock PHASE R/W D7 Command W LOCK 0 Result (19) Sense Drive Status PHASE R/W D7 Command Result R (20) Invalid PHASE R/W D7 Command W Result R 5.2 Register Descriptions There are several status, data, and control registers in W83977F/G, W83977AF/AG. These registers ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: 7 INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A In PS/2 Model 30 mode, the bit definitions for this register are as follows INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5.2.2 Status Register B (SB Register) (Read base address + 1) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A This bit indicates the status of DSB output pin. DSA (Bit 5): This bit indicates the status of DSA output pin. WD F/F(Bit 4): This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin. RDATA F/F(Bit 3): This bit indicates the complement of the latched RDATA output pin ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A If three mode FDD function is enabled (EN3MODE = 1 in Logical Device 0 CRF0 bit:0), the bit definitions are as follows: 7 Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of Logical Device 0 CRF1 bit 4,5. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5.2.5 Main Status Register (MS Register) (Read base address + 4) The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows 5.2.6 Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A PRECOMP DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC = 1 01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Status Register 0 (ST0) 7 1-0 4 Status Register 1 (ST1 Status Register 2 (ST2 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected NR Not Ready: 1 Drive is not ready 0 Drive is ready EC Equipment Check: ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Status Register 3 (ST3) 7 5.2.8 Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes PC/ only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A In the PS/2 Model 30 mode, the bit definitions are as follows: DSKCHG (Bit 7): This bit indicates the status of DSKCHG input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 5.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6. UART PORT 6.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five- bit format only) or two stop bits ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A TABLE 6-1 UART Register Bit Map REGISTER ADDRESS BASE + 0 Receiver RBR RX Data Buffer BDLAB = Bit 0 Register 0 (Read Only Transmitter TBR TX Data Buffer BDLAB = Bit 0 Register 0 (Write Only Interrupt ICR RBR Data Control Ready BDLAB = Register Interrupt 0 Enable ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the bit is reset, an odd number of logic 1's are sent or checked. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese two cases, this bit will be reset to a logical 0. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A (3) Modem input pins are isolated from the communication link and connect internally as DTR (bit 0 of HCR) → DSR , RTS ( bit 1 of HCR) → CTS , Loopback RI input ( bit 2 of HCR) → RI and IRQ enable ( bit 3 of HCR) → DCD . ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6.2.5 UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits Bit 7, 6: These two bits are set to a logical 1 when UFR bit Bit 5, 4: These two bits are always logic 0. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6.2.7 Interrupt Control Register (ICR) (Read/Write) This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 6.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 6-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER PRE-DIV: 13 PRE- DIV:1.625 1.8461M HZ 14.769M HZ 50 400 75 600 110 880 134.5 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7. INFRARED (IR) PORT The Infrared (IR) function provides point-to-point (or multi-point to multi-point) wireless communication which can operate under various transmission protocols including IrDA 1.0 SIR, IrDA 1.1 MIR (1.152 Mbps), IrDA 1.1 FIR (4 Mbps), SHARP ASK-IR, and remote control (NEC, RC-5, advanced RC-5, and RECS-80 protocol) ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A SET 0 Legacy/Advanced IR Control and Status Registers. 1 Legacy Baud Rate Divisor Register. 2 Advanced IR Control and Status Registers. 3 Version ID and Mapped Control Registers. 4 Transmitter/Receiver/Timer Counter Registers and IR Control Registers. 5 Flow Control and IR Control and Frame Status FIFO Registers Physical Layer Control Registers 7 Remote Control and IR front-end Module Selection Registers ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.2.2 Set0.Reg1 - Interrupt Control Register (ICR) MODE B7 B6 Legacy Advanced IR ETMRI EFSFI The advanced IR functions including Advanced SIR/ASK-IR, MIR, FIR, or Remote IR are described as follows. Bit 7: Legacy IR Mode: Not used. A read will return 0. Advanced IR Mode: ETMRI - Enable Timer Interrupt A write to 1 will enable timer interrupt ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt A write to 1 will enable USR interrupt or enable transmitter underrun interrupt. Bit 1: ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt A write to 1 will enable the transmitter buffer register empty interrupt. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A TABLE: INTERRUPT CONTROL FUNCTION ISR Bit 3 Bit 2 Bit 1 Bit 0 Interrupt priority First Second Second Third ** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1. Advanced IR: Bit 7: TMR_I - Timer Interrupt. Set to 1 when timer count to logical 0. This bit is valid when: (1) the timer registers are defined in Set4.Reg0 and Set4.Reg1 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 2: Advanced SIR/ASK-IR modes: USR_I - IR Status Interrupt. Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and registered in the IR Status Register (USR). Cleared to 0 when USR is read. MIR, FIR modes: FEND_I - Frame End Interrupt. ...
Page 62
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR bit Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be cleared to logical 0 by itself after being set to logical 1 ...
Page 63
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): These two registers share the same address. In all Register Sets, Set Select Register (SSR) can be programmed to select a desired Set but IR Control Register can only be programmed in Set 0 and Set 1. In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control Register ...
Page 64
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A AD_MD2~0 (BIT 000 001 010 011 100 101 110 111 Bit 4: MIR, FIR Modes: SIR_PLS - Send Infrared Pulse Writing 1 to this bit will send a 2 signal to SIR that the high speed infrared is still in. This bit will be auto cleared by hardware ...
Page 65
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.2.6 Set0.Reg5 - IR Status Register (USR) MODE B7 B6 Legacy IR RFEI TSRE Advanced IR LB_INFR TSRE Reset Value 0 Legacy IR Register: These registers are defined the same as previous description. Advanced IR Register: Bit 7: MIR, FIR Modes: LB_INFR - Last Byte In Frame End Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame from another when RX FIFO has more than one frame ...
Page 66
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Legacy IR Register: This is a temporary register that can be accessed and defined by the user. Advanced IR Register: Bit 7 MIR, FIR Modes: FLC_ACT - Flow Control Active Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that this will be affected by Set5 ...
Page 67
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.3 Set1 - Legacy Baud Rate Divisor Register ADDRESS REGISTER OFFSET NAME 0 BLL 1 BHL 2 ISR/UFR 3 UCR/SSR 4 HCR 5 USR 6 HSR 7 UDR/ESCR 7.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode. ...
Page 68
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.4.1 Reg0 Advanced Baud Rate Divisor Latch (ABLL/ABHL) These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward operation from occurring. ...
Page 69
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 1: DMA_F - DMA Fairness DMA_F 0 1 Bit 0: ADV_SL - Advanced Mode Select A write to 1 selects advanced mode. 7.4.3 Reg3 - Sets Select Register (SSR) Reading this register returns E0H. Writing a value selects Register Set. REG. BIT 7 BIT 6 SSR SSR7 ...
Page 70
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A RX_FSZ1 Bit 1, 0: TX_FSZ1~0 - Transmitter FIFO Size 1~0 These bits setup transmitter FIFO size when FIFO is enable. TX_FSZ1 TABLE: SIR Baud Rate BAUD RATE FROM DIFFERENT PRE-DIVIDER PRE-DIV: 13 PRE-DIV:1.625 1.8461M HZ 14.769M HZ 50 400 75 600 110 880 134.5 ...
Page 71
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) MODE BIT 7 BIT 6 Advanced IR 0 Reset Value 0 Bit 7~6: Reserved, Read 0. Bit 5~0: Reading these bits returns the current transmitter FIFO depth, that is, the number of bytes left in the transmitter FIFO. ...
Page 72
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.5.2 Reg1 - Mapped IR Control Register (MP_UCR) This register is read only. Reading this register returns IR Control Register value of Set 0. REG. BIT 7 BIT 6 SSR SSR7 SSR6 Default Value 0 0 7.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR) This register is read only. Reading this register returns IR FIFO Control Register (UFR) value of SET ...
Page 73
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) MODE BIT 7 BIT 6 Advanced Reset Value 0 0 Bit 7~4: Reserved, write to 0. Bit 3, 2: IR_MSL1 Infrared Mode Select Select legacy IR, SIR, or ASK-IR mode. Note that in legacy SIR/ASK-IR user should set DIS_BACK=1 to avoid backward when programming baud rate. ...
Page 74
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A These are combined 13-bit register. Writing these registers programs the transmitter frame length of a package. These registers are only valid when APM=1 (automatic package mode, Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length if the transmitted data is larger than the programmed frame length ...
Page 75
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) These registers control flow control mode operation as shown in the following table. REG. BIT 7 BIT 6 FC_MD FC_MD2 FC_MD1 Reset 0 0 Value Bit 7~5 FC_MD2 - Flow Control Mode When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR (Handshake Status Register) ...
Page 76
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.7.3 Set5.Reg3 - Sets Select Register (SSR) Writing this register selects Register Set. Reading this register returns ECH. REG. BIT 7 BIT 6 SSR SSR7 SSR6 Default Value 1 7.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1) REG. BIT 7 BIT 6 IRCFG1 - FSF_TH Reset ...
Page 77
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO) This register shows the bottom byte of frame status FIFO. REG. BIT 7 BIT 6 FS_FO FSFDR LST_FR Reset 0 0 Value Bit 7: FSFDR - Frame Status FIFO Data Ready Indicate that a data byte is valid in frame status FIFO bottom. ...
Page 78
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Receiver Frame Length FIFO (RFLFL/RFLFH): These are combined 13-bit register. Reading these registers returns received byte count for the frame. When read, the register of RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). Lost Frame Number (LST_NU): When LST_FR=1 (Set5 ...
Page 79
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 5: FIR_CRC - FIR (4M bps) CRC Type FIR_CRC Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer. Bit 4: MIR_CRC - MIR (1.152M/0.576M bps) CRC Type MIR_CRC Bit 2: INV_CRC - Inverting CRC When set to 1, the CRC is inversely output in physical layer. ...
Page 80
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 7.8.3 Set6.Reg2 - SIR Pulse Width REG. BIT 7 BIT 6 SIR_PW - Reset Value 0 This 5-bit register sets SIR output pulse width. S_PW4~0 00000 01101 Others 7.8.4 Set6.Reg3 - Set Select Register Select Register Set by writing a set number to this register. Reading this register returns F0H. ...
Page 81
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 3~0: F_FG3~0 - FIR Beginning Flag Number These bits define the number of transmitter Preamble Flag in FIR. Note that the number of FIR start flag should be equal to sixteen which is defined in IrDA 1.1 physical layer. The default value is 16. M_FG3~0 ...
Page 82
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A This register defines frequency range of receiver of remote IR. Bit 7~5: RX_FR2~0 - Receiver Frequency Range 2~0. These bits select the input frequency range of the receiver implemented through a band pass filter, i.e., only the input signals whose frequency lies in the range defined in this register will be received ...
Page 83
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Table: High Frequency range select of receiver RX_FSL4~0 00011 01000 01011 Note that those unassigned combinations are reserved. Table: SHARP ASK-IR receiver frequency range select. RX_FR2~0 001 - 480.0* 533.3* 457.1 564.7 Note that those unassigned combinations are reserved. ...
Page 84
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Table: Low frequency selected. TX_FSL4~0 00011 00100 ... 11101 Note that those unassigned combinations are reserved. Table: High frequency selected. TX_FSL4~0 00011 01000 01011 Note that those unassigned combinations are reserved. 7.9.3 Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) REG ...
Page 85
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 5: RXCFS - Receiver Carry Frequency Select RXCFS 0 1 Bit 4: Reserved, write 0. Bit 3: TX_CFS - Transmitter Carry Frequency Select. Select low speed or high speed transmitter carry frequency. TX_FCS 0 1 Bit 2: RX_DM - Receiver Demodulation Mode. RX_DM 0 1 Bit 1~0: TX_MM1~0 - Transmitter Modulation Mode 1~0 ...
Page 86
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 7: IR_MSP - IR Mode Select Pulse When set to 1, the transmitter (IRTX) will send a 64 end operational mode. transmitter IR pulse (IRTX) to switch between high speed IR (such as FIR or MIR) and low speed IR (SIR or ASK-IR), this bit should be used. Bit 6~4: SIR_SL2~0 - SIR (Serial IR) mode select ...
Page 87
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 7: Reserved, write 0. Bit 6~4: LRC_SL2~0 - Low Speed Remote IR mode select. These bits setup the operational mode of low speed remote IR front-end module when AM_FMT=1 and AD_MD2~0 are configured to Remote IR mode. These values will be automatically loaded to IR_SL2~0, respectively. ...
Page 88
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Table: IR receiver input pin selection IRSL0D IRX_MSL Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M bps) and FIR (4M bps), (3) IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver. ...
Page 89
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8. PARALLEL PORT 8.1 Printer Interface Logic The parallel port of the W83977F/G, W83977AF/AG makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977F/G, W83977AF/AG supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
Page 90
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A TABLE 8-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER CONNECTOR OF W83977F 8.2 Enhanced Parallel Port (EPP) TABLE 8-2 PRINTER MODE AND EPP REGISTER ADDRESS Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. ...
Page 91
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows: Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the print head is changing position, or during an error state ...
Page 92
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: Bit 7, 6: These two bits are a logic one during a read. They can be written. ...
Page 93
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. Bit definitions of each data port are as follows: When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of IOW causes an EPP data write cycle to be performed, and the trailing edge of IOW latches the data for the duration of the EPP write cycle ...
Page 94
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.2.7 EPP Pin Descriptions EPP NAME TYPE nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. nWait I Inactive to acknowledge that data transfer is completed. Active to indicate that the device is ready for the next transfer ...
Page 95
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3 Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions ...
Page 96
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3.2 Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host ...
Page 97
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. ...
Page 98
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned ...
Page 99
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3.10 ecr (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: 7 Bit 7-5: These bits are read/write and select the mode. 000 Standard Parallel Port mode. The FIFO is reset in this mode. ...
Page 100
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 2: Read/Write 1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts has occurred, the serviceIntr bit is set hardware. This bit must be reset re-enable the interrupts. Writing this bit will not cause an interrupt. ...
Page 101
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3.12 ECP Pin Descriptions NAME TYPE nStrobe (HostClk) PD<7:0> I/O nAck (PeriphClk) Busy (PeriphAck) PError (nAckReverse) Select (Xflag) nAutoFd (HostAck) nFault (nPeriphRequest) nInit (nReverseRequest) nSelectIn (ECPMode) 8.3.13 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation ...
Page 102
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.3.13.1 Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010). ...
Page 103
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 8.4 Extension FDD Mode (EXTFDD) In this mode, the W83977F/ AF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1. ...
Page 104
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 9. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL The RTC with 242 bytes of RAM is a low-power device that provides a time-of-day clock in various formats, and a calendar with century register. It has two alarms and three programmable interrupts also equipped with external battery backup capability for keeping time and saving RAM data under power-failure situation ...
Page 105
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A TABLE 9.1.2 - REAL TIME CLOCK ADDRESS MAP BANK 1 ADDRESS REGISTER TYPE 00h-7Fh R/W Bank 2 has 13 registers, 1 Century register, 8 Alarm B registers and 4 control/status registers for " On- Now " function. TABLE 9.1.3 - REAL TIME CLOCK "ON-NOW" ADDRESS MAP BANK 2 ...
Page 106
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Time, Calendar, Alarm A, and Alarm B data Modes continued REGISTER FUNCTION LOCATION Register 05h Hours Alarm A (12-Hour Mode) (24-Hour Mode) Register 06h Day of Week Register 07h Date of Month Register 08h Month Register 09h Year Register 40h Century Register 41h Sec ...
Page 107
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Update Period and UIP Timing 9.3 REGISTERS The RTC has four control/status registers. They are accessible at all times. 9.3.1 Register 0Ah • All bits are unaffected by RESET. • Register read/write register except bit 7 (UIP is read only). BIT ...
Page 108
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A PERIODIC INTERRUPT RATE TABLE RS[3: 9.3.2 Register 0Bh (Read/Write) BIT 7 6 NAME SET PE SET When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h, Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the update cycle function occurs once per second ...
Page 109
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG "1" on this bit enables the update-ended flag (UF) bit in register C to assert an interrupt. A "0" on this bit prohibits update-ended interrupt. The UE bit is cleared by setting the SET bit RESET. DM The data mode bit determines whether time and calendar updates are in binary format or in binary- coded-decimal (BCD) format. A " ...
Page 110
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A UF The update-ended interrupt flag bit is set after the end of each update cycle. This bit is cleared by a RESET or when this bit is read. Bit 3 - Bit 0 These bits are reserved and all read "0". 9.3.4 Register D (Read only) BIT 7 6 VRT ...
Page 111
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 9.7 Registers 9.7.1 On-Now”” Register 1 (Bank2 Register 49h) BIT 7 6 NAME PF CLPOST PF (Power Failure) The PF is set when a power-failure occurs. This bit is cleared by writing a "1" to it. CLPOST (Clear Panel-switch-off-Save Timer) This bit is self-cleared after writing an "1" set, Panel-switch-off-Save timer is stopped and cleared ...
Page 112
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 9.7.2 On-Now_ Register 2 (Bank2 Register 4Ah) BIT 7 6 NAME MCLKE KCLKE MCLKE (Mouse Clock Enable) Logical 1 on this bit, a falling edge transition on MCLK asserts PSCTRL . KCLKE (Keyboard Clock Enable) Logical 1 on this bit, a falling edge transition on KCLK asserts PSCTRL . ...
Page 113
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 9.7.3 "On-Now" Register 3 (Bank2 Register 4Bh) BIT 7 6 NAME PHRIST Reserved This register is read only except bit 5. PHRIST ( PHRI Status) This bit holds the current value of PHRI . PSPOFD (Panel Switch Power-Off Detect) Logical 1 on this bit, a Panel-Switch-Off event is detected. ...
Page 114
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 9.7.4 "On-Now" Register 4 (Bank2 Register 4Ch) BIT 7 6 NAME PSOFDS1 PSOFDS0 This register is read only except bits 5, 6 and 7. PSOFDS1, PSOFDS0 These two bits decide the delay time between panel switch power off event and power supply off. ...
Page 115
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 10. KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977F/G, W83977AF/AG is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM ® - compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
Page 116
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 10.1 Output Buffer The output buffer is an 8-bit read-only register at I/O address 60H (Default, PnP programmable I/O address LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer can only be read when the output buffer full bit in the register is " ...
Page 117
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 10.4 Commands COMMAND 20h Read Command Byte of Keyboard Controller 60h Write Command Byte of Keyboard Controller Test Password A4h Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded A5h Load Password Load Password until a "0" is received from the system ...
Page 118
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Commands, continued COMMAND ABh Interface Test ADh Disable Keyboard Interface AEh Enable Keyboard Interface C0h Read Input Port(P1) and send data to the system C1h Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts the upper four bits of Port1 into STATUS register ...
Page 119
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A HGA20 (Hardware GATE A20) A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal. A "0" on this bit disables hardware GATEA20 control logic function. HKBRST (Hardware Keyboard Reset) A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal. ...
Page 120
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 11. GENERAL PURPOSE I/O W83977F/G, W83977AF/AG provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 14 GP I/O ports are divided into two groups, the first group contains 8 ports, and the other group contains only 6 ports. ...
Page 121
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 11.1 Basic I/O functions The Basic I/O functions of W83977F/G, W83977AF/AG provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available in the second group of the GP I/O port). ...
Page 122
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Table 11.1.1 I/O BIT ENABLE INT BIT 0 = OUTPUT 0 = DISABLE 1 = INPUT 1 = ENABLE Table 11.1.2 GP I/O PORT ACCESSED REGISTER GP1 GP2 POLARITY BIT BASIC I/O OPERATIONS 0 = NON INVERT 1 = INVERT 0 Basic non-inverting output 1 Basic inverting output 0 Non-inverted output bit value of GP2 ...
Page 123
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 11.2 Alternate I/O Functions W83977F/G, W83977AF/AG provides several alternate functions which are scattered among the GP I/O ports. Table 11.2.1 shows their assignments. Polarity bit can also be set to alter their polarity of alternate functions. Table 11.2.1 GP I/O PORT GP10 ...
Page 124
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 11.2.3 Power LED The Power LED function provides 1 Hertz rate toggle pulse output with 50 percent duty cycle. Table 11.2.2 shows how to enable Power LED. Table 11.2.2 WDT_CTRL1 BIT[1] WDT_CTRL0 BIT[ Note: Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers. ...
Page 125
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 12. PLUG AND PLAY CONFIGURATION The W83977F/G, W83977AF/AG provides many configuration registers for setting up different types of configurations. There are two approaches to entering the configuration state and accessing these configuration registers, Comply PnP and Compatible PnP. The Comply PnP protocol is based on the Plug and Play ISA Specification ...
Page 126
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 12.1.2 Sleep State In this state, Plug and Play wait for a Wake[CSN] command. This command will selectively enable one or more cards to enter either the Isolation or Configure states based on the write data and the value of the CSN on each card. If the write data for the Wake[CSN] command is zero then all cards that have not been assigned a CSN will enter the Isolation state ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 12.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83977F/ AF enters the default operating mode. Before the W83977F/ AF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13. CONFIGURATION REGISTER 13.1 Chip (Global) Control Register CR00 (only available in comply PnP mode) Bit 7-0 : IORDPRA9 - IORDPRA2 --> Set RD_DATA Port A9-A2 CR01 (only available in comply PnP mode) Bit7-0 : SISO 7-0 --> Serial Isolation CR02 (Default 0x00) Bit 7-3 : Reserved. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG Power down = 1 No Power down CR23 (Default 0x00) Bit7-6 : Reserved Bit 5-3 : APDTMS2 APDTMS1 APDTMS0 = 000 4 seconds count-down time of the APD mode. = 001 8 seconds count-down time of the APD mode. = 010 16 seconds count-down time of the APD mode. = 011 32 seconds count-down time of the APD mode ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit 2 : IRTRI [W83977AF only] Bit 1 : Reserved. Bit 0 : FDCTRI. CR26 (Default 0b0s000000) Bit 7 : SEL4FDD = 0 Select two FDD mode Select four FDD mode. Bit 6 : HEFRAS These two bits define how to enable Configuration mode. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG Disable IRQ Sharing = 1 Enable IRQ Sharing Bit 3 :Reserved Bit 2-0 : PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 [W83977AF only] Bit 7-0 : CPSIDB7 - CPSIDB0 --> Comply PnP Serial ID Bit 7 - Bit 0. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 4-3 : PIN70S1, PIN70S0 SMI = GP21 = 10 8042 P16 RIC = 11 [W83977AF only] Bit 2-1 : PIN69S1, PIN69S0 PHRI = GP20 = 10 Reserved = 11 Reserved Bit 0 : PIN58S = 0 KBLOCK = 1 GP13 CR2C (Default 0x00) Bit 7-6 : PIN121S1, PIN121S0 = 00 DRQ0 = 01 GP17 = 10 8042 P14 = 11 nDTRC [W83977AF only] ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.2 Logical Device 0 (FDC) CR30 (Default 0x01) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60 (Default 0x03, 0xf0) These two registers select FDC I/O base address [0x100:0xFF8 byte boundaries ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG Swap (Default Drive and Motor sel 0 and 1 are swapped. Bit 3-2 Interface Mode = 11 AT Mode (Default (Reserved PS Model 30 Bit 1 : FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0 : Floppy Mode = 0 Normal Floppy Mode (Default Enhanced 3-Mode FDD ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A DTYPE1 DPYTE0 Note: X means don't care. CRF4 (Default 0x00) FDD0 Selection: Bit 7 : Reserved. Bit 6 : Precomp. Disable Disable FDC Precompensation Enable FDC Precompensation. Bit 5 : Reserved. Bit 4-3 : DRTS1, DRTS0 : Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A TABLE A DRIVE RATE TABLE SELECT DRTS1 DRTS0 Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 DMOD1 DRVDEN0(PIN 13.3 Logical Device 1 (Parallel Port) CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit Activates the logical device. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CR60 (Default 0x03, 0x78 at PNPCSV=0) These two registers select Parallel Port I/O base address. [0x100:0xFFC byte boundaries(EPP not supported) or [0x100:0xFF8 byte boundaries(all modes supported, EPP is only available when the base address 8byte boundary). CR70 (Default 0x07 when PNPCSV=0 at POR) Bit 7-4 : Reserved ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.4 Logical Device 2 (UART A)¢) CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60 (Default 0x03, 0xF8 when PNPCSV=0 at POR ) These two registers select Serial Port 1 I/O base address [0x100:0xFF8 byte boundaries ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.5 Logical Device 3 (UART B) CR30 (Default 0x01 when PNPCSV=0 at POR) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60 (Default 0x02, 0xF8 when PNPCSV=0 at POR) These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundaries ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.6 Logical Device 4 (Real Time Clock) CR30 (Default 0x01 when PENKRC=1 at POR) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.7 Logical Device 5 (KBC) CR30 (Default 0x01 when PENKRC=1 at POR) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enables I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60 (Default 0x00, 0x60 when PENKRC=1 at POR) These two registers select the first KBC I/O base address [0x100:0xFFF byte boundaries ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG Select 16Mhz as KBC clock input. Bit 5-3 : Reserved. Bit Port 92 disable Port 92 enable. Bit Gate20 software control Gate20 hardware speed up. Bit KBRST software control KBRST hardware speed up. 13.8 Logical Device 6 (IR) CR30 (Default 0x00) Bit 7-1 : Reserved. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CR74 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for RX of UART C. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = 0x03 DMA3 = 0x04-0x07 No DMA active CR75 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for TX of UART C. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 13.9 Logical Device 7 (Auxiliary I/O Part I) CR30 (Default 0x00) Bit 7-1 : Reserved. Bit Activates the logical device Logical device is inactive. CR31 Bit 7-2 : Reserved. Bit 1 : ENRNGCK -- > Enable I/O Range check Bit 0 : FORIORD --> Forces LDN to respond I/O read CR60 (Default 0x00, 0x00) These two registers select GP1 I/O base address [0x100:0xFFF byte boundaries ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CRE0 (GP10, Default 0x01) Bit 7-5 : Reserved. Bit 4 : IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3 : Select Function Select Alternate Function : Interrupt Steering Select Basic I/O Function. Bit 2 : Reserved. Bit 1 : Polarity Invert Invert. Bit 0 : In/Out selection. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CRE3 (GP13, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function Select Basic I/O function Select 1st alternate function : Power LED output Reserved = 11 Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert Invert Bit 0 : In/Out : 1 : Input Output CRE4 (GP14, Default 0x01) Bit 7-5 : Reserved ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CRE7 (GP17, Default 0x01) Bit 7-4 : Reserved. Bit 4-3 : Select Function Select Basic I/O function Select 1st alternate function : Power LED output. Please refer to TABLE Reserved Bit 2 : Reserved. Bit 1 : Polarity : 1 : Invert Invert Bit 0 : In/Out : 1 : Input Output TABLE C ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A CR60 (Default 0x00, 0x00) These two registers select GP2 & Watch Dog I/O base address [0x100:0xFFE byte boundaries. I/O base address + 1 : Watch Dog I/O base address. CR70 (Default 0x00) Bit 7-4 : Reserved. Bit 3-0 : These bits select IRQ resource for Common IRQ of GP20~GP25 at Logic Device 9. ...
Page 149
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 2 : Int Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity : 1 : Invert Invert Bit 0 : In/Out : 1 : Input Output CREA (GP22, Default 0x01) Bit 7-5 : Reserved. Bit 4-3 : Select Function Select Basic I/O function Reserved = 10 Select 2nd alternate function : Keyboard P14 I/O. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 2 : Int Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity : 1 : Invert Invert Bit 0 : In/Out : 1 : Input Output CRED (GP25, Default 0x01) Bit 7-4 : Reserved. Bit 3 : Select Function Select alternate function: GATE A20(Connect to KBC P21 Select basic I/O function ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Bit 3 : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output Enable = 0 Disable Bit 2 : Mouse interrupt reset Enable or Disable = 1 Watching Dog Timer is reset upon a Mouse interrupt = 0 Watching Dog Timer is not affected by Mouse interrupt Bit 1 : Keyboard interrupt reset Enable or Disable ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14. SPECIFICATIONS 14.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A DC CHARACTERISTICS, continued PARAMETER SYM. I CMOS level bi-directional pin with source-sink capability Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL I CMOS level bi-directional pin with source-sink capability ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A DC CHARACTERISTICS, continued PARAMETER SYM. I/O 12t - TTL level bi-directional pin with source-sink capability Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A DC CHARACTERISTICS, continued PARAMETER CMOS level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage CMOS level Schmitt-triggered input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage ...
Page 156
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3 AC Characteristics 14.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SA9-SA0, AEN, DACK , CS , setup time to IOR ↓ SA9-SA0, AEN, DACK , hold time for IOR ↑ IOR width Data access time from IOR ↓ Data hold from IOR ↓ ...
Page 157
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec, continued. PARAMETER IOW or IOR response time from DRQ TC width RESET width INDEX width DIR setup time to STEP DIR hold time from STEP STEP pulse width STEP cycle width WD pulse width ...
Page 158
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.2 UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt IOR Delay from Reset Interrupt Delay from Initial IRQ Reset to Transmit Start IOW Delay from to Reset interrupt IOW Delay from Initial to interrupt Delay from Stop to Set Interrupt IOR ...
Page 159
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.4 EPP Data or Address Read Cycle Timing Parameters PARAMETER IOR Ax Valid to Asserted IOR IOCHRDY Deasserted to Deasserted IOR Deasserted to Ax Valid IOR IOR Deasserted to IOW or IOR Asserted to IOCHRDY Asserted PD Valid to SD Valid IOR Deasserted to SD Hi-Z (Hold Time) ...
Page 160
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.5 EPP Data or Address Write Cycle Timing Parameters PARAMETER Ax Valid to IOW Asserted SD Valid to Asserted IOW Deasserted to Ax Invalid WAIT Deasserted to IOCHRDY Deasserted Command Asserted to WAIT Deasserted IOW Deasserted to IOW or IOR Asserted IOCHRDY Deasserted to IOW Deasserted WAIT Asserted to Command Asserted ...
Page 161
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.6 Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active 14.3.7 ECP Parallel Port Forward Timing Parameters ...
Page 162
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.9 KBC Timing Parameters NO. T1 Address Setup Time from WRB T2 Address Setup Time from RDB T3 WRB Strobe Width T4 RDB Strobe Width T5 Address Hold Time from WRB T6 Address Hold Time from RDB T7 Data Setup Time T8 Data Hold Time ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 14.3.10 GPIO, ACPI, ROM Interface Timing Parameters SYMBOL t Write data to GPIO update WGO t SWITCH pulse width SWP t SWE Delay from SWITCH events to PSCTRL , and from SWITCH Off event to SMI t PORW SMI pulse width (edge mode) t POWR Delay from APCI Reg.1 write to SMI inactive ...
Page 164
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15. TIMING WAVEFORMS 15.1 FDC Processor Read Operation SA0-SA9 AEN CS TAR DACK IOR TFD D0-D7 IRQ Processor Write Operation SA0-SA9 AEN TAW DACK IOW D0-D7 IRQ DMA Operation TAM DRQ DACK TMA TMRW IOW or IOR TMW (IOW) TMR (IOR) ...
Page 165
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.2 UART/Parallel SIN (RECEIVER INPUT DATA) IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) Transmitter Timing STAR DATA (5-8) ...
Page 166
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.2.1 Modem Control Timing IOW (WRITE MCR) RTS,DTR │ CTS,DSR │ DCD │ → ← │ IRQ3 or IRQ4 IOR (READ MSR) RI ACK IRQ7 MODEM Control Timing │ │ │ → ← TMWO │ │ │ │ │ ...
Page 167
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3 Parallel Port 15.3.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ -159 - Publication Release Date: May 2006 Revision 0.60 ...
Page 168
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3.2 EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t17 t21 t25 t27 t26 -160 t15 t19 t20 t28 ...
Page 169
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3.3 EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 -161 - t12 t14 t21 Publication Release Date: May 2006 ...
Page 170
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3.4 EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT t18 t21 t25 t26 t27 -162 t15 t19 t20 t28 ...
Page 171
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3.5 EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 15.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t19 t20 t1 t2 >| t6 >| ...
Page 172
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.3.7 ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 15.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD -164 ...
Page 173
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.4 KBC 15.4.1 Write Cycle Timing A2, CSB WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND 15.4.2 Read Cycle Timing A2,CSB AEN RDB D0-D7 15.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT ACTIVE ...
Page 174
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.4.4 Receive Data from K/B CLOCK (KCLK) T15 SERIAL DATA START (T1) T20 15.4.5 Input Clock CLOCK CLOCK T21 15.4.6 Send Data to Mouse MCLK T25 MDAT START Bit 15.4.7 Receive Data from Mouse MCLK T29 MDAT START T14 ...
Page 175
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 15.5 GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 15.6 Master Reset (MR) Timing Vcc MR 15.7 ACPI PANSW 15.7.1 Trigger and V OH PANSW V OL HI-Z PSCTRL V OL HI- SMI VALID VALID PREVIOUS STATE tVMR Timing PSCTRL tSWP tSWP ...
Page 176
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A RIA RIB 15.7 KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and RIA, RIB V OH KCLK, MCLK V OL PWAKIN1, PWAKIN2 HI-Z PSCTRL V OL PHRI 15.7.3 Trigger and V OH PHRI V OL HI-Z PSCTRL V OL Timing PSCTRL tRINW tRINW tRTO -168 Timing ...
Page 177
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 16. APPLICATION CIRCUITS 16.1 Parallel Port Extension FDD 13 WE2/SLCT 25 12 WD2/ MOB2/BUSY 23 10 DSB2/ACK 22 9 PD7 21 8 PD6 20 7 PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram ...
Page 178
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 16.2 Parallel Port Extension 2FDD 13 WE2/SLCT 25 12 WD2/ MOB2/BUSY 23 10 DSB2/ACK 22 9 DSA2/PD7 21 8 MOA2/PD6 20 7 PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 16 ...
Page 179
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 17. ORDERING INFORMATION PART NO. W83977F-P W83977F-A W83977AF-P W83977AF-A W83977G-A W83977AG-A KBC FIRMWARE TM without FIR, 3rd UART Phoenix MultiKey/42 TM without FIR, 3rd UART AMIKEY-2 TM with FIR, 3rd UART Phoenix MultiKey/42 TM with FIR, 3rd UART AMIKEY-2 TM Lead-free version of W83977F-A AMIKEY-2 ...
Page 180
... W83977G-A AM. MEGA. 87-96 520AB26519520 1st line: Winbond logo 2nd line: the type number: W83977G-A 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: Tracking code 520 : packages made in '05, week assembly house ID; A means ASE, S means SPIL revision; B means version B, C means version C ...
Page 181
... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A 19. PACKAGE DIMENSIONS (128-pin QFP 102 65 103 128 See Detail F y Seating Plane Detail F -173 - Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom Max A 0.25 0.35 0.45 0.010 0.014 0.018 1 A 2.57 2.72 2.87 0.101 0.107 ...
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... W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life ...