MT46V32M16P-5B:J Micron Technology Inc, MT46V32M16P-5B:J Datasheet - Page 49

• Manufacturer Part Number: MT46V32M16P-5B:J
• Description: IC SDRAM 512MB 200MHZ 66TSOP
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT46V32M16P-5B:J

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 35:
DESELECT
NO OPERATION (NOP)
LOAD MODE REGISTER (LMR)
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. O; Core DDR Rev. D 2/11 EN
CKE
H
H
L
L
n-1
CKE
Truth Table 5 – CKE
Notes 1–6 apply to the entire table; Notes appear below
H
H
L
L
n
Notes:
Current State
Bank(s) active
All banks idle
All banks idle
Power-down
Power-down
Self refresh
Self refresh
1. CKE
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
6. Once initialized, including during self refresh mode, V
7. Upon exit of the self refresh mode, the DLL is automatically enabled. A minimum of 200
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in
progress are not affected.
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
The mode registers are loaded via inputs A0–An (see "REGISTER DEFINITION" on page
57). The LMR command can only be issued when all banks are idle, and a subsequent
executable command cannot be issued until
clock edge.
MAND
HIGH until after the read postamble time (
write recovery time (
ified range.
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the
n
is the logic state of CKE at clock edge n; CKE
n
.
n
is the command registered at clock edge n, and ACTION
See Table 30 on page 45
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
t
WR) has been met.
Command
X
X
49
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RPST); for a WRITE, CKE must stay HIGH until the
t
MRD is met.
512Mb: x4, x8, x16 DDR SDRAM
Precharge power-down entry
n-1
Active power-down entry
Maintain power-down
Maintain self refresh
was the state of CKE at the previous
REF
Exit power-down
Self refresh entry
Exit self refresh
must be powered within the spec-
Action
©2000 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
t
XSNR period.
Commands
Notes
7