MT41J128M8JP-15E:G Micron Technology Inc, MT41J128M8JP-15E:G Datasheet - Page 147

• Manufacturer Part Number: MT41J128M8JP-15E:G
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR3 SDRAMr

Specifications of MT41J128M8JP-15E:G

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 220mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 95: WRITE (BC4 OTF) to PRECHARGE
DQ Input Timing
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Command 1
DQS, DQS#
Address 3
DQ 4
CK#
CK
WRITE
Bank,
Col n
T0
Notes:
NOP
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. The write recovery time (
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
Figure 86 on page 141 shows the strobe to clock timing during a WRITE. DQS, DQS#
must transition within 0.25
data mask setup and hold timings are measured relative to the DQS, DQS# crossing, not
the clock crossing.
The WRITE preamble and postamble are also shown. One clock prior to data input to the
DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven
LOW (DQS# is driven HIGH) during the WRITE preamble,
be kept LOW by the controller after the last data is written to the DRAM during the
WRITE postamble,
Data setup and hold times are shown in Figure 96 on page 148. All setup and hold times
are measured from the crossing points of DQS and DQS#. These setup and hold values
pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by
times.
the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank.
NOP
T2
WL = 5
NOP
T3
t
WPST.
NOP
T4
t
WR) is referenced from the rising clock edge at T9.
t
t WPRE
CK of the clock transitions as limited by
147
NOP
T5
DI
n
n + 1
DI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
n + 2
T6
DI
n + 3
1Gb: x4, x8, x16 DDR3 SDRAM
DI
t WPST
NOP
T7
Indicates A Break In
Time Scale
t
WPRE. Likewise, DQS must
©2006 Micron Technology, Inc. All rights reserved.
NOP
T8
Transitioning Data
t
DQSH and
t
DQSS. All data and
NOP
T9
Operations
t
WR specifies
t WR 2
t
DQSL.
Don’t Care
Valid
PRE
Tn