MT41J1G4THD-15E:D Micron Technology Inc, MT41J1G4THD-15E:D Datasheet
MT41J1G4THD-15E:D
Specifications of MT41J1G4THD-15E:D
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MT41J1G4THD-15E:D Summary of contents
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TwinDie TM DDR3 SDRAM MT41J1G4 – 64 Meg Banks x 2 Ranks MT41J512M8 – 32 Meg Banks x 2 Ranks For component data sheets, refer to Micron’s Web site: Functionality The 4Gb ...
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Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address PDF: 09005aef83188bab/Source: 09005aef83169de6 MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN 1024 Meg Meg banks x 2 ranks 8K 32K A[14:0] 8 ...
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Ball Assignments and Descriptions Figure 1: 82-Ball FBGA Ball Assignments – Rev. A (Top View DDQ C V SSQ D V REFDQ E ODT1 F ODT0 G CS1 ...
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Figure 2: 78-Ball FBGA Ball Assignments – Rev. D (Top View DDQ C V SSQ D V REFDQ E ODT1 F ODT0 G CS1 ...
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... READ/WRITE commands, to select one location out A10/AP, A[9:0] of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command ...
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Table 3: 82-Ball and 78-Ball FBGA Ball Descriptions (continued) Symbol Type Description V Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. DDQ V Supply Reference voltage for control, command, and address: V REFCA all ...
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Functional Description The 4Gb (TwinDie) DDR3 SDRAM is a high-speed, CMOS dynamic random access mem- ory device containing 4,294,967,296 bits and is internally configured as two 8-bank 2Gb DDR3 SDRAM. Although each die is tested individually within the dual-die package, ...
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Functional Block Diagrams Figure 3: Functional Block Diagram (64 Meg Banks x 2 Ranks) CS1# CAS# CKE1 RAS# ODT1 WE# ZQ1 RESET# Figure 4: Functional Block Diagram (32 Meg Banks x 2 ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the device data sheet ...
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Table 5: Thermal Characteristics Parameter/Condition Operating case temperature Notes: 1. MAX operating case temperature. T (see Figure 5 thermal solution must be designed to ensure the DRAM device does not exceed the max- imum T 3. Device functionality ...
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I Specifications and Conditions DD Table 7: DDR3 I Specifications and Conditions – Rev. A CDD Note 1 applies to the entire table. Combined Symbol Individual Die Status I I CDD0 CDD0 I I CDD1 CDD1 I I CDD2P0 CDD2P0 ...
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Table 8: DDR3 I Specifications and Conditions – Rev. D CDD Note 1 applies to the entire table. Combined Symbol Individual Die Status I I CDD0 CDD0 I I CDD1 CDD1 I I CDD2P0 CDD2P0 (slow exit CDD2P1 ...
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Package Dimensions Figure 6: 82-Ball FBGA Package Dimensions – Rev. A Seating plane A 0.1 A 12.5 ±0.1 82X Ø0.45 Dimensions apply to solder balls post-reflow. Pre- reflow ball is Ø0. Ø0.33 NSMD ball ...
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Figure 7: 78-Ball FBGA Package Dimensions – Rev. D Seating plane A 0.12 A 78X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post reflow on Ø0.35 SMD ball pads. 9.6 CTR 0.8 TYP 0.8 ...