DS33W11+ Maxim Integrated Products, DS33W11+ Datasheet - Page 102
![IC MAPPING ETHERNET 256CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS33W11+
Manufacturer Part Number
DS33W11+
Description
IC MAPPING ETHERNET 256CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33W11+
Applications
Data Transport
Interface
Parallel/Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
256-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 9-3. Example Functional Timing: DS2155 T1 Transmit-Side Boundary Timing
*
Figure 9-4. Example Functional Timing: DS2155 E1 Receive-Side Boundary Timing
*
Figure 9-5. Example Functional Timing: DS2155 T1 Receive-Side Boundary Timing
*
When interfacing to a Maxim T1/E1 transceiver as shown, the device should be programmed to invert the RCLK
input for each serial interface (LI.RCR1.RCLKINV = 1).
Because the first gapped transmit clock input edge after the transmit sync pulse is coincident with the start of the
first byte of user data, the transmit sync setup control bits must be configured for a sync pulse that arrives zero
clock cycles early ( LI.TCR.TS_SETUP[1:0] = 00).
Rev: 063008
Note DS2155 TCLK shown only for comparative purposes.
Note DS2155 RCLK shown only for comparative purposes.
Note DS2155 RCLK shown only for comparative purposes.
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
RCHCLK
RCHCLK
TCHCLK
TSYNC
RSYNC
RSYNC
RSER
RSER
TSER
RCLK
RCLK
TCLK
LSB
CHANNEL 32
TIME SLOT 24
X
MSB
TIME SLOT 1
LSB
LSB
MSB
F
MSB
FRAMING BYTE / CHANNEL 0
LSB MSB
TIME SLOT 1
TIME SLOT 2
LSB
MSB
LSB
MSB
CHANNEL 1
TIME SLOT 2
LSB MSB
102 of 375
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