DS33W11+ Maxim Integrated Products, DS33W11+ Datasheet - Page 369
![IC MAPPING ETHERNET 256CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS33W11+
Manufacturer Part Number
DS33W11+
Description
IC MAPPING ETHERNET 256CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33W11+
Applications
Data Transport
Interface
Parallel/Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
256-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.5 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
Figure 13-3. JTAG Functional Timing
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
(STATE)
JTRST
Output
JTCLK
(INST)
JTDO
JTMS
•
•
•
•
•
JTDI
Pin
The JTAG controller starting from reset state.
Shifting out the first 4 LSB bits of the IDCODE.
Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern.
Shifting the TDI pin to the TDO pin through the bypass shift register.
An asynchronous reset occurs while shifting.
Reset
X
Run Test
Idle
Select DR
Scan
Capture
DR
IDCODE
Shift
DR
X
Exit1
DR
Update
DR
Output pin level change if in "EXTEST" instruction mode
Select DR
Scan
Select IR
Scan
Capture
IR
Shift IR
X
Exit1
IR
Update
IR
X
Select DR
Scan
Capture
DR
BYPASS
Shift
DR
369 of 375
Logic Idle
X
IDCODE
X
Test
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