DS33X161+ Maxim Integrated Products, DS33X161+ Datasheet - Page 77

• Manufacturer Part Number: DS33X161+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X161+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.17.1.5WAN-VLAN Trapping
When trapping frames received on the WAN interface by VLAN ID, the user configures the VLAN IDs (VIDs) to be
trapped using the WAN-VLAN Table. Trapping is then enabled or disabled with the SU.WEM.WEVIT bit. See
Section 8.16 for more information on VLAN configuration. Only one WAN Group Decapsulator can be allowed to
forward frames to the WAN Extract Queue at a time (determined by user configuration). If VLAN Trapping is
enabled, and the 4-bit value returned from the WAN-VLAN Table indicates “Extract”, but the port that the frame is
associated with has not been configured to forward to the WAN Extract queue, then the “Extract” status returned
from the WAN-VLAN Table is ignored. For more details on WAN-VLAN Table programming, see Section 8.16.2.
8.17.1.6WAN Ethernet Type Trapping
When trapping frames received on the WAN interface by Ethernet Type, the user can configure and 2-byte
Ethernet Type Field to be trapped in the SU.WEET register. Trapping is then enabled or disabled with the
SU.WEM.WEETT bit. The WAN Ethernet Type trap is valid only with frame formats in which the Ethernet Type
occurs in the first 32 bytes. Thus, the WAN Ethernet Type trap is not valid with the following frame types:
8.17.1.7WAN Header Trapping
Trapping can also be performed on any two consecutive bytes within the first 8 bytes of frames received from the
WAN interface. When trapping frames received on the WAN interface by header, the user configures a 2-byte
value to be trapped in the SU.WEHT register. The offset is configured in the SU.WEHTP register. Trapping is then
enabled or disabled with the SU.WEM.WEHT bit.
8.17.2 Frame Extraction and Frame Insertion
Extraction of trapped frames through the microport is done one byte at a time, with the beginning of the frame
being read first. The device must be configured to properly trap frames as described in Section 8.17.1. The user
may enable an interrupt to alert the host processor that a frame is available for extraction via the GL.MSIER3
interrupt enable register. A latched status register (GL.MLSR3) may also be used as indication that a frame is
available for extraction. When a trapped frame is available, the user must select the correct FIFO with the
GL.MCR1 register. The user must then read the length of the frame from GL.MSR1 or GL.MSR2 in order to know
how many bytes to extract. The user then reads one byte at a time from the FIFO read access register
(GL.MFARR) to extract the entire frame. When the entire frame has been read, the user indicates that the frame
may be discarded from the FIFO with the GL.MFAWR.RD_DN bit.
Steps for Frame Extraction:
1. Read the GL.MSR3 LAN/WAN FIFO Extraction Available Status bit to verify FIFO has a frame to be read.
2. Select the corresponding FIFO via GL.MCR1.
3. Read the size of frame in bytes from GL.MSR1 or GL.MSR2.
4. Read the frame from the GL.MFARR register one byte at a time.
5. Write a 0-to-1 transition to GL.MFAWR.RD_DN.
6. Repeat step 1.
Insertion of a frame through the host microport is done one byte at a time, with the beginning of the frame written
first. The user must first configure the LAN insertion settings and enable insertion via the SU.LIM register, or
configure the WAN insertion settings and enable insertion via the AR.MQC register. The correct FIFO must then be
selected with the GL.MCR1 register. The length of the frame to be inserted must then be written into GL.MCR2 or
GL.MCR3. The user proceeds to write one byte of the frame at a time to the FIFO access register, GL.MFAWR,
beginning with the first byte of the frame. Each write to this address automatically increments the pointer of the
selected FIFO. When the entire frame has been written, the GL.MFAWR.WR_DN bit is used to indicate that the
frame is ready for transmission.
Steps for Frame Insertion:
1. Configure the LAN insertion settings in the SU.LIM register, or WAN insertion settings in AR.MQC.
2. Read the GL.MSR3 LAN/WAN Queue Empty Status bit to verify FIFO is empty.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
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4-byte Encapsulation Header with Q-in-Q & std VLAN & LLC/SNAP (HDLC or GFP-Null)
8-byte Encapsulation Header with Q-in-Q & std VLAN & LLC/SNAP (HDLC or GFP-Linear)
8-byte Encapsulation Header with std VLAN & LLC/SNAP (HDLC or GFP-Linear)
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