DS33X161+ Maxim Integrated Products, DS33X161+ Datasheet - Page 88

• Manufacturer Part Number: DS33X161+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X161+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
immediately after the cHEC bytes when in GFP mode or after the start flag when in HDLC mode. This bit should be
set to 1 for X.86, cHDLC and GFP transport. This bit should be equal to 0 for HDLC traffic with no headers.
The Decapsulator can be configured to remove a MPLS tag prior to forwarding to the LAN interface. The 4-byte
removal function used for this purpose is enabled using the PP.DMCR.DR2E control bit. When enabled, 4 bytes
are removed after the first remove (DR1E) function. Note that PP.DMCR.DR1E must be properly configured for this
function to operate correctly.
The Decapsulator can be configured to remove a VLAN tag prior to forwarding to the LAN interface. The 4-byte
removal function used for this purpose is enabled using the PP.DMCR.DR3E control bit. When enabled, 12 bytes
are skipped (Ethernet DA/SA) and the following 4 bytes are removed. This function is performed after the
Decapsulator Remove Function 1 and/or Decapsulator Remove Function 2 have been performed. When
Decapsulator Remove Functions 1 and 2 are disabled, 12 bytes are skipped from the beginning of the Ethernet
frame.
To optimize WAN bandwidth in point-to-point applications, Ethernet header information may be removed from the
datagram during WAN transport. The Decapsulator can be configured to replace the missing Ethernet header
information prior to forwarding to the LAN interface, by inserting a 14 or 18 byte values to each incoming frame.
This function is enabled using the PP.DMCR.DAE[1:0] control bits. When enabled, a 14-byte value from the
PP.DA1DR through PP.DA7DR registers or a 18-byte value from the PP.DA1DR through PP.DA9DR registers will
be inserted after the cHEC bytes in GFP mode, or after the HDLC header/flag when in HDLC mode. Once all
packet processing is performed by the Decapsulator, the Ethernet frames are forwarded to the MAC for
transmission on the LAN interface.
Note that some devices in the product family have less than four Decapsulators. The DS33X11 contains only
Decapsulator #1. The DS33W41 and DS33X42 contain only Decapsulators #1 and #3.
Rev: 063008
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