MT18HTF12872PDZ-667G1 Micron Technology Inc, MT18HTF12872PDZ-667G1 Datasheet - Page 12

• Manufacturer Part Number: MT18HTF12872PDZ-667G1
• Description: MODULE DDR2 SDRAM 1GB 240RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTF12872PDZ-667G1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
Table 10: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
PDF: 09005aef83d3d893
htf18c128_256_512x72pdz.pdf - Rev. D 11/10 EN
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
DD
RAS =
OUT
DD
DD
DD
t
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
); CKE is LOW; Other control and address bus inputs are stable;
),
DD
= 0mA; BL = 4, CL = CL (I
Specifications
t
RP =
), AL = 0;
DD
t
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
t
RP (I
t
DD
DD
CK =
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
CK (I
Specifications and Conditions – 1GB, Die Revision G
t
CK =
DD
t
DD
CK =
),
t
), AL = 0;
CK (I
t
RC =
t
CK (I
DD4W
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DD
t
RC (I
); REFRESH command at every
DD
t
CK =
),
DD
t
RAS =
),
t
t
CK (I
RAS =
t
CK =
t
RAS MAX (I
t
DD
CK =
t
CK =
t
),
RAS MIN (I
t
CK =
t
t
CK (I
RAS =
t
t
OUT
CK (I
CK =
t
t
CK (I
CK =
12
t
DD
CK
= 0mA; BL = 4, CL =
DD
DD
t
),
t
DD
RAS MAX (I
CK (I
t
DD
),
),
t
CK (I
); CKE is HIGH, S#
RAS =
t
t
),
RP =
RC =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
RFC (I
t
RCD =
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
); CKE is
t
t
RAS MAX
RP (I
RC (I
DD
DD
t
RCD
) inter-
),
DD
DD
t
RP
);
),
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
1
1
2
2
2
2
2
2
2
2
2
© 2009 Micron Technology, Inc. All rights reserved.
I
-80E/
DD
1188
1143
-800
648
738
126
432
504
324
162
594
918
126
Specifications
1098
1053
-667
603
693
126
396
450
270
162
540
873
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA