MT18HVF25672PZ-80EH1 Micron Technology Inc, MT18HVF25672PZ-80EH1 Datasheet - Page 12

• Manufacturer Part Number: MT18HVF25672PZ-80EH1
• Description: MOD DDR2 SDRAM 2GB 240RDIMM VLP
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HVF25672PZ-80EH1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 800MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12: DDR2 I
Values shown for MT47H512M4 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 4) com-
ponent data sheet
PDF: 09005aef83d74fdb
hvf18c128_256_512x72pz.pdf – Rev. C 11/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
t
tween valid commands; Address bus inputs are stable during deselects; Data bus
inputs are switching
RCD (I
CK (I
RP (I
OUT
RP =
OUT
RC =
DD
),
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
DD
t
t
t
RAS =
DD
RP (I
RC (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DD
DD
t
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
),
t
RRD =
t
RP (I
t
CK =
DD
DD
t
Specifications and Conditions – 4GB (Die Revsion C)
RRD (I
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
t
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
DD
t
), AL = 0;
), AL =
CK (I
),
),
t
t
RC =
RCD =
t
DD
CK =
1GB, 2GB, 4GB (x72, SR) 240-Pin DDR2 SDRAM VLP RDIMM
); REFRESH command at every
t
RCD (I
t
DD4W
RC (I
t
t
CK =
t
RCD (I
CK (I
DD
DD
t
),
DD
CK (I
) - 1 ×
DD
t
),
RAS =
); CKE is HIGH, S# is HIGH be-
t
CK =
t
RAS =
t
DD
CK =
t
CK =
t
),
CK (I
t
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
t
OUT
t
CK (I
CK =
t
RAS MAX (I
DD
t
CK (I
CK =
12
DD
);
= 0mA; BL = 4, CL
DD
t
t
),
t
DD
RAS MAX (I
CK =
CK (I
t
),
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
CK (I
); CKE is HIGH,
RAS =
DD
t
RC =
t
DD
t
),
RFC (I
CK (I
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
),
); CKE is
t
RAS
RC
DD
t
DD
RP =
DD
),
)
),
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
© 2010 Micron Technology, Inc. All rights reserved.
IDD Specifications
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-800
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Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA