MT18VDDT12872AG-40BJ1 Micron Technology Inc, MT18VDDT12872AG-40BJ1 Datasheet - Page 11

• Manufacturer Part Number: MT18VDDT12872AG-40BJ1
• Description: MODULE DDR SDRAM 1GB 184UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18VDDT12872AG-40BJ1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Features: -
• Package / Case: 184-UDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef80814e61/Source: 09005aef807f8acb
DD18C64_128x72A.fm - Rev. D 9/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
changing once per clock cycle; Vin = Vref for DQ, DQS, and DM
Active power-down standby current: One device bank active;
Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
READ or WRITE commands
CK =
RC =
CK =
CK =
t
t
t
t
t
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
RC (MIN);
CK (MIN); CKE = HIGH; Address and other control inputs
CK (MIN); Address and control inputs change only during active
CK =
CK =
t
RC =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
RAS (MAX);
Idd Specifications and Conditions – 1GB
Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
t
CK =
Notes:
t
t
CK =
CK =
t
CK (MIN); Iout = 0mA; Address and control
OUT
t
t
t
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
in Idd2P (CKE LOW) mode.
t
CK (MIN); DQ, DM, and DQS inputs
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM
t
RC =
t
t
t
RC =
REFC =
REFC = 7.8125µs
t
RC (MIN);
t
RC (MIN);
t
11
RFC (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
Idd4W
Idd3N
Idd5A
Idd2P
Idd3P
Idd4R
Idd2F
Idd0
Idd1
Idd5
Idd6
Idd7
1
1
2
2
1
2
2
2
1
2
2
1
1,440
1,710
1,080
1,755
1,800
6,210
4,095
-40B
990
810
198
90
90
Electrical Specifications
1,215
1,485
1,530
1,620
5,220
3,690
-335
810
630
900
180
90
90
©2004 Micron Technology, Inc. All rights reserved
1,215
1,485
1,530
1,440
5,220
3,645
-262
810
630
900
180
90
90
-26A/
1,080
1,350
1,350
1,260
5,040
3,195
-265
720
540
810
180
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA