UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 30

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
Table 7.
Table 8.
UJA1069_3
Product data sheet
Bit
15 and 14
13
12
11 to 7
6 and 5
4
3
2
1 and 0
Bit
15 and 14
13
12
11
10
9
8
System Diagnosis register bit description
Interrupt Enable and Interrupt Enable Feedback register bit description
Symbol
A1, A0
RRS
RO
-
LINFD[1:0]
V3D
-
V1D
-
Symbol
A1, A0
RRS
RO
WTIE
OTIE
-
SPIFIE
6.12.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the
SBC.
Description
register address
Read Register Select
Read Only
reserved
LIN failure diagnosis
V3 diagnosis
reserved
V1 diagnosis
reserved
Description
register address
Read Register Select
Read Only
Watchdog Time-out
Interrupt Enable
Over-Temperature
Interrupt Enable
reserved
SPI clock count Failure
Interrupt Enable
[1]
Rev. 03 — 10 September 2007
Value
00
1
1
0
0 0000
11
10
01
00
1
0
1
1
0
00
Value
01
1
0
1
0
1
0
1
0
0
1
0
Function
read System Diagnosis register
read System Diagnosis register without writing to Mode
register
read System Diagnosis register and write to Mode register
reserved for SBCs with CAN transceiver
TXDL is clamped dominant
LIN is shorted to GND (dominant clamped)
LIN is shorted to VBAT (recessive clamped)
no failure
OK
fail; V3 is disabled due to an overload situation
reserved for SBCs with another voltage regulator
OK; V1 always above V
fail; V1 was below V
again with read access
reserved for SBCs with CAN transceiver
Function
select the Interrupt Enable register
read the Interrupt register
read the Interrupt Enable Feedback register
read the register selected by RRS without writing to
Interrupt Enable register
read the register selected by RRS and write to Interrupt
Enable register
a watchdog overflow during Standby causes an interrupt
instead of a reset event (interrupt based cyclic wake-up
feature)
no interrupt forced on watchdog overflow; a reset is forced
instead
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
reserved for SBCs with CAN transceiver
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
UV(VFI)
LIN fail-safe system basis chip
UV(VFI)
since last read access; bit is set
since last read access
UJA1069
© NXP B.V. 2007. All rights reserved.
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