UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 33

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
Table 10.
[1]
[2]
Table 11.
UJA1069_3
Product data sheet
Bit
12
11 and 10
9
8
7 and 6
5
4
3
2
1
0
Bit
15 and 14
13
RLC is set automatically with entering Restart mode or Fail-safe mode. This guarantees a safe reset period in case of serious failure
situations. External reset spikes are lengthened by the SBC until the programmed reset length is reached.
If WEN is not set, the WAKE port is completely disabled. There is no change of the bits EWS and WLS within the System Status
register.
System Configuration and System Configuration Feedback register bit description
Physical Layer Control and Physical Layer Control Feedback register bit description
Symbol
RO
-
-
RLC
V3C[1:0]
-
V1CMC
WEN
WSC
ILEN
ILC
Symbol
A1, A0
RRS
6.12.9 Physical Layer Control register and Physical Layer Control Feedback
register
These registers allow configuration of the LIN transceiver of the SBC and allow the
settings to be read back.
Description
Read Only
reserved
reserved
Reset Length Control
V3 Control
reserved
V1 Current Monitor
Control
Wake Enable
Wake Sample Control
INH/LIMP Enable
INH/LIMP Control
Description
register address
Read Register Select
[2]
Rev. 03 — 10 September 2007
Value
1
0
00
0
1
0
11
10
01
00
0
1
0
1
0
1
0
1
0
1
0
Value
11
1
0
[1]
Function
read register selected by RRS without writing to System
Configuration register
read register selected by RRS and write to System
Configuration register
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
reserved for SBCs with CAN transceiver
t
t
Cyclic mode 2; t
Cyclic mode 1; t
continuously ON
OFF
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
an increasing V1 current causes a reset if the watchdog
was disabled during Standby mode
an increasing V1 current just reactivates the watchdog
during Standby mode, and an interrupt is forced (if enabled)
WAKE pin enabled
WAKE pin disabled
Wake mode cyclic sample
Wake mode continuous sample
INH/LIMP pin active (See ILC bit)
INH/LIMP pin floating
INH/LIMP pin HIGH if ILEN bit is set
INH/LIMP pin LOW if ILEN bit is set
Function
select Physical Layer Control register
read the General Purpose Feedback register 1
read the Physical Layer Control Feedback register
RSTNL
RSTNL
long reset lengthening time selected
short reset lengthening time selected
w(CS)
w(CS)
long period; see
short period; see
LIN fail-safe system basis chip
…continued
Figure 13
UJA1069
Figure 13
© NXP B.V. 2007. All rights reserved.
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