UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 6

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
UJA1069_3
Product data sheet
5.2 Pin description
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
n.c.
n.c.
n.c.
TEST
INH/LIMP
WAKE
n.c.
n.c.
n.c.
n.c.
GND
n.c.
LIN
RTLIN
BAT14
n.c.
SYSINH
Pin description
Pin
HTSSOP32 HTSSOP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Rev. 03 — 10 September 2007
1
-
2
3
4
5
6
7
8
9
10
11
-
-
-
12
13
14
-
-
-
-
15
16
17
18
19
20
21
Description
not connected
not connected
LIN transmit data input (LOW for dominant, HIGH for
recessive)
voltage regulator output for the microcontroller (3 V, 3.3 V
or 5 V depending on the SBC version)
LIN receive data output (LOW when dominant, HIGH
when recessive)
reset output to microcontroller (active LOW; will detect
clamping situations)
interrupt output to microcontroller (active LOW;
open-drain, wire-AND this pin to other ECU interrupt
outputs)
enable output (active HIGH; push-pull, LOW with every
reset / watchdog overflow)
SPI data input
SPI data output (floating when pin SCS is HIGH)
SPI clock input
SPI chip select input (active LOW)
not connected
not connected
not connected
test pin (should be connected to ground in application)
inhibit / limp home output (BAT14 related, push-pull,
default floating)
local wake-up input (BAT42 related, continuous or cyclic
sampling)
not connected
not connected
not connected
not connected
ground
not connected
LIN bus line (LOW in dominant state)
LIN-bus termination resistor connection
14 V battery supply input
not connected
system inhibit output (BAT42 related; e.g. for controlling
external DC-to-DC converter)
LIN fail-safe system basis chip
UJA1069
© NXP B.V. 2007. All rights reserved.
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