UJA1069TW24/3V3:51 NXP Semiconductors, UJA1069TW24/3V3:51 Datasheet - Page 40

• Manufacturer Part Number: UJA1069TW24/3V3:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V3:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3.3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280014518; UJA1069TW24/3V3-T; UJA1069TW24/3V3-T

NXP Semiconductors
7. Limiting values
Table 24.
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
[1]
[2]
[3]
[4]
[5]
UJA1069_3
Product data sheet
Symbol
V
V
V
V
I
T
T
T
V
WAKE
stg
amb
vj
BAT42
BAT14
DC(n)
trt
esd
Only relevant if V
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T
is a fixed value to be used for the calculation of T
ambient temperature (T
Human Body Model (HBM): C = 100 pF; R = 1.5 k .
ESD performance according to IEC 61000-4-2 (C = 150 pF, R = 330 ) of pins LIN, RTLIN, WAKE, BAT42 and V3 with respect to GND
was verified by an external test house. Following results were obtained:
a) Equal or better than 4 kV (unaided)
b) Equal or better than 20 kV for pin LIN (using external ESD protection: NXP Semiconductors PESD1LIN diode)
Machine Model (MM): C = 200 pF; L = 0.75 H; R = 10 .
Limiting values
Parameter
BAT42 supply voltage
BAT14 supply voltage
DC voltage on pins
transient voltage at pin LIN
DC current at pin WAKE
storage temperature
ambient temperature
virtual junction temperature
electrostatic discharge voltage
V1
V3 and SYSINH
INH/LIMP
SENSE
WAKE
LIN and RTLIN
TXDL, RXDL, SDO, SDI, SCK, SCS,
RSTN, INTN and EN
TEST
WAKE
< V
amb
GND
).
0.3 V; current will flow into pin GND.
vj
Rev. 03 — 10 September 2007
. The rating for T
Conditions
load dump; t
V
with respect to any other pin
in accordance with
ISO 7637-3
HBM
MM; at any pin
BAT42
continuous
load dump; t
at pins LIN, RTLIN,
WAKE, BAT42, V3,
SENSE; with respect to
GND
at any other pin
V
vj
BAT14
limits the allowable combinations of power dissipation (P
500 ms
500 ms
1 V
[1]
[2]
[3]
[4]
[5]
vj
= T
LIN fail-safe system basis chip
Min
-
-
0.3
0.3
0.3
1.5
0.3
0.3
1.5
60
0.3
0.3
150
15
55
40
40
8.0
2.0
200
amb
+ P
d
R
th(vj-amb)
Max
+60
+60
+33
+45
+5.5
V
V
V
+60
+60
V
+15
+100
-
+150
+125
+150
+8.0
+2.0
+200
UJA1069
BAT42
BAT42
BAT42
V1
© NXP B.V. 2007. All rights reserved.
+ 0.3
, where R
+ 0.3
+ 0.3
+ 1.2
d
) and
40 of 64
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
kV
kV
V
th(vj-amb)
C
C
C