74LVC4066BQ,115 NXP Semiconductors, 74LVC4066BQ,115 Datasheet - Page 14

IC SWITCH QUAD SPST 14DHVQFN

74LVC4066BQ,115

Manufacturer Part Number
74LVC4066BQ,115
Description
IC SWITCH QUAD SPST 14DHVQFN
Manufacturer
NXP Semiconductors
Series
74LVCr
Type
Analog Switchr
Datasheet

Specifications of 74LVC4066BQ,115

Package / Case
14-VFQFN Exposed Pad
Function
Switch
Circuit
4 x SPST - NO
On-state Resistance
6 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
1.65 V ~ 5.5 V
Current - Supply
0.1µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Switch Configuration
SPST
On Resistance (max)
34 Ohm (Typ) @ 1.95 V
On Time (max)
5.3 ns (Typ) @ 1.95 V
Off Time (max)
4.2 ns (Typ) @ 1.95 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Switch Current (typ)
0.0001 mA @ 3.3 V
Package
14DHVQFN EP
Maximum On Resistance
195@1.95V Ohm
Maximum Propagation Delay Bus To Bus
0.8(Typ)@1.95V|0.4(Typ)@2.7V|0.3(Typ)@3.6V|0.2(Typ)@5.5V ns
Maximum Low Level Output Current
50 mA
Maximum Turn-off Time
4.2(Typ)@1.95V ns
Maximum Turn-on Time
5.3(Typ)@1.95V ns
Switch Architecture
SPST
Power Supply Type
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3019-2
935273744115

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC4066BQ,115
Manufacturer:
NXP Semiconductors
Quantity:
2 400
NXP Semiconductors
Table 11.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); T
74LVC4066
Product data sheet
Symbol
Q
Fig 18. Test circuit for measuring total harmonic distortion
Fig 19. Test circuit for measuring the frequency response when switch is in ON-state
inj
Test conditions:
V
V
Adjust f
V
V
CC
CC
CC
CC
Additional dynamic characteristics
Parameter
charge injection
= 1.65 V: V
= 2.3 V: V
= 3 V: V
= 4.5 V: V
10.2.1 Test circuits
i
voltage to obtain 0 dBm level at output. Increase f
i
= 2.5 V (p-p).
i
i
= 2 V (p-p).
= 4 V (p-p).
i
= 1.4 V (p-p).
f i
V
IH
V
IH
0.1 μF
f i
All information provided in this document is subject to legal disclaimers.
50 Ω
C
Conditions
f
i
L
= 1 MHz; R
V
V
V
V
V
nY/nZ
= 0.1 nF; V
CC
CC
CC
CC
CC
600 Ω
nY/nZ
nE
Rev. 4 — 24 November 2010
…continued
= 1.8 V
= 2.5 V
= 3.3 V
= 4.5 V
= 5.5 V
nE
V
L
CC
V
gen
= 1 M; see
CC
= 0 V; R
i
frequency until dB meter reads 3 dB.
nZ/nY
nZ/nY
0.5V
0.5V
gen
Figure 23
CC
R L
= 0 ;
CC
R L
C L
C L
10 μF
001aag492
dB
D
001aag491
V
O
amb
V
Min
-
-
-
-
-
O
= 25
Typ
3.3
4.1
5.0
6.4
7.5
74LVC4066
C.
Quad bilateral switch
© NXP B.V. 2010. All rights reserved.
Max
-
-
-
-
-
Unit
pC
pC
pC
pC
pC
14 of 23

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