SI2438FT18-EVB Silicon Laboratories Inc, SI2438FT18-EVB Datasheet - Page 125
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SI2438FT18-EVB
Manufacturer Part Number
SI2438FT18-EVB
Description
BOARD EVAL SI2438+SI3018 24PIN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-E-FM.pdf
(128 pages)
Specifications of SI2438FT18-EVB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 125 of 128
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Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions (Continued)
Dimension
ZE
ZD
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in milllimeters (mm) unless
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994
3. This Land Pattern Design is based on IPC-SM-782
4. All dimensions shown are at Maximum Material Condition
1. All pads are to be non-solder mask defined (NSMD).
1. A stainless steel, laser-cut and electro-polished stencil with
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1
4. A 1.45 x 1.45 mm square aperture should be used for the
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC
otherwise noted.
specification.
guidelines.
(MMC). Least Material Condition (LMC) is calculated based
on a Fabrication Allowance of 0.05 mm.
Clearance between the solder mask and the metal pad is to
be 60 m minimum, all the way around the pad.
trapezoidal walls should be used to assure good solder
paste release.
for the perimeter pads.
center pad. This provides approximately 70% solder paste
coverage on the pad, which is optimum to assure correct
component stand-off.
J-STD-020C specification for Small Body Components.
Rev. 1.4
MIN
—
—
Si3050 + Si3011/18/19
MAX
3.31
3.31
125
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