SI2438FT18-EVB Silicon Laboratories Inc, SI2438FT18-EVB Datasheet - Page 13
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI2438FT18-EVB
Manufacturer Part Number
SI2438FT18-EVB
Description
BOARD EVAL SI2438+SI3018 24PIN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-E-FM.pdf
(128 pages)
Specifications of SI2438FT18-EVB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 9. Switching Characteristics—GCI Highway Serial Interface
(V
Parameter
Cycle Time PCLK (Single Clocking Mode)
Cycle Time PCLK (Double Clocking Mode)
Valid PCLK Inputs
FSYNC Period
PCLK Duty Cycle
PCLK Jitter Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tri-State
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
Notes:
D
=
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
3.0 to 3.6 V, T
times are referenced to the 20% and 80% levels of the waveform.
1
2
FSYNC
DRX
PCLK
DTX
A
Figure 5. GCI Highway Interface Timing Diagram (1x PCLK Mode)
=
0 to 70 °C, C
t
d1
t
su1
L
=
20 pF)
t
h1
3
Symbol
t
t
t
t
t
jitter
jitter
t
t
t
t
t
su1
su2
t
t
t
dty
d1
d2
d3
h1
h2
t
t
fp
p
p
r
f
t
su2
Rev. 1.4
t
d2
t
p
Conditions
t
h2
t
fp
Test
Si3050 + Si3011/18/19
t
r
Min
40
25
20
25
20
—
—
—
—
—
—
—
—
—
—
—
—
IH
=
V
O
– 0.4 V, V
2.048
4.096
Typ
488
244
125
50
t
—
—
—
—
—
—
—
—
—
—
—
f
t
d3
IL
=
0.4 V, rise and fall
±120
Max
60
25
25
20
20
20
—
—
—
—
—
—
—
—
—
2
Units
MHz
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
13
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