SI2438FT18-EVB Silicon Laboratories Inc, SI2438FT18-EVB Datasheet - Page 41
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SI2438FT18-EVB
Manufacturer Part Number
SI2438FT18-EVB
Description
BOARD EVAL SI2438+SI3018 24PIN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3050-E-FM.pdf
(128 pages)
Specifications of SI2438FT18-EVB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 41 of 128
- Download datasheet (888Kb)
By setting the correct starting point of the data, the Si3050 can operate with buses having multiple devices
requiring different time slots. The DTX pin is high impedance except during transmission of an 8-bit PCM sample.
DTX returns to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of
PCLK following the LSB. This behavior is based on the setting of the TRI bit in the PCM Mode Select register.
Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the
risk of driver contention. In addition to 8-bit data modes, a 16-bit linear mode is also provided. This mode can be
activated via the PCMF bits in the PCM Mode Select register. Double-clocked timing also is supported in which the
duration of a data bit is two PCLK cycles. This mode is activated via the PHCF bit in the PCM Mode Select register.
Setting the TXS or RXS registers greater than the number of PCLK cycles in a sample period stops data
transmission or reception. Figures 30–33 illustrate the usage of the PCM highway interface to adapt to common
PCM standards.
Figure 30. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission
PCLK_CNT
FSYNC
PCLK
DRX
DTX
HI-Z
0
1
MSB
MSB
2
3
(TXS = RXS = 0, PHCF = 0, TRI = 1)
4
5
6
Rev. 1.4
7
8
LSB
LSB
9
Si3050 + Si3011/18/19
10
11
12
HI-Z
13
14
15
16
17
18
41
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