CY8CKIT-050 Cypress Semiconductor Corp, CY8CKIT-050 Datasheet - Page 76

• Manufacturer Part Number: CY8CKIT-050
• Description: DEV KIT PSOC 5 CY8C55
• Manufacturer: Cypress Semiconductor Corp
• Series: PSoC®5r
• Type: MCUr

Specifications of CY8CKIT-050

• Design Resources: PSoC 5 Dev Kit Schematic CY8CKIT-050 PCBA BOM CY8CKIT-50 Gerber File
• Contents: Board, Cable, CD, Display, Documentation
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: CY8C55
• Other names: 428-3110

11.5.2 Delta-Sigma ADC
Unless otherwise specified, operating conditions are:
■
■
■
■
Table 11-20. 20-bit Delta-sigma ADC DC Specifications
Document Number: 001-66235 Rev. *A
Ge
Gd
Vos
TCVos
PSRRb
CMRRb
INL20
DNL20
INL16
DNL16
INL12
DNL12
INL8
DNL8
Rin_Buff
Notes
Parameter
29. Based on device characterization (not production tested).
30. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional
Operation in continuous sample mode
fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Gain error
Gain drift
Input offset voltage
Temperature coefficient, input offset
voltage
Input voltage range, single ended
Input voltage range, differential unbuf-
fered
Input voltage range, differential,
buffered
Power supply rejection ratio, buffered
Common mode rejection ratio, buffered
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
Integral non linearity
Differential non linearity
ADC input resistance
[29]
[29]
Description
[29]
[29]
[29]
[29]
[29]
[29]
[29]
[29]
PRELIMINARY
[29]
[29]
[29]
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V, 16-bit mode
Buffered, 16-bit mode, V
25 °C
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16-bit,
Range = ±1.024 V
Buffer gain = 1, 16 bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Range = ±1.024 V, unbuffered, using
external clock source
Input buffer used
Conditions
PSoC
DDA
®
5: CY8C55 Family Datasheet
= 2.7 V,
V
V
V
Min
90
85
10
SSA
SSA
SSA
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
GPIO/2
DDA
No. of
No. of
GPIO
V
V
Page 76 of 114
Max
±0.2
±0.5
±32
20
50
55
±1
±2
±1
±1
±1
±1
±1
DDA
DDA
–
–
–
–
– 1
µV/°C
ppm/°
Units
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
bits
mV
MΩ
dB
dB
%
C
V
V
V
–
–
–
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