ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 20

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

ADC1412D080 test
ADC0
ADC1
NXP Semiconductors
Table 7.
Content of file is shown as table format
QS_ADC1412D_10.doc
Quick start
Name
175.00
175.00
(MHz)
Fin
Dynamic results as stored in a text file
3.3.6.1 FFT spectrum
(MHz)
80.00
80.00
Fs
Before proceeding to any acquisition, the user needs to do the following entries:
Note that ADC0 and ADC1 refer to the acquisition path on the HSDC-EXTMOD board. It
corresponds respectively to the bottom and top ADC of the ADC1412D, ADC1212D and
ADC1112D series.
Note that while acquisition is running, any other action (ADC SPI programming, quit or
refresh) is not possible. Stop acquisition first before proceeding to any other task.
The first graph to be displayed is the FFT spectrum of the digital pattern acquired:
(dBFS)
-86.74
-1.08
Vin
the sampling frequency Fs: 80 Msps in our example (field
the input frequency Fin: 175 MHz in our example for both ADC channels (field
the number of samples to be acquired 16384 in our example (field
indicate whether it is CMOS or LVDS DDR (field
press the “INITIALIZATION” button
indicate whether Fin or Fs are coherent or not (field
press the “ACQUIRE” button
results fields
the “Display …” button (“Display ADC0” or “Display ADC1” or “Display ADC0 &
ADC1”).
press “STOP” button to stop acquisition;
field
analysis;
field
header as a comment and browse to indicate where to store data file.
how data are stored:
FPGA is ready (red LED is flashing ¼ on and ¾ off) ;
PLL embedded is locked (green LED is on);
if signals are coherent, selected which Fin or Fs are fixed for the calculation (see
appendix
if signals are not coherent, select the window for FFT processing to apply (the
Blackman window gives better results).
ENOB
11.10
-5.89
-
allows to do FFT averaging over up to 255 trials, suitable for small signal
allows to store dynamic results to text file. Click on the check box, enter a
SINAD
-33.71
(dBc)
68.84
A.1);
will be updated automatically depending on the display choice using
Rev. 10 — 17 December 2010
Quick start ADC1412D, ADC1212D, ADC1112D series
SNR_C
-33.71
(dBc)
68.56
SNR_FS
(dBFS)
69.93
53.04
to display the results from the FFT processing. The
SFDR_C
-19.91
(dBc)
83.04
. It will initialized the HSDC-EXTMOD board:
SFDR_FS
(dBFS)
84.12
66.84
);
-80.59
(dBc)
THD
4.77
):
-103.19
-84.17
(dBc)
);
H2
© NXP B.V. 2010. All rights reserved.
-119.04
-86.48
(dBc)
H3
);
Table 7
Quick start
-106.34
-111.66
(dBc)
H4
shows
20 of 27
);
-110.96
-92.16
(dBc)
H5
-100.45
-120.78
(dBc)
H6