74HCT4067DB,112 NXP Semiconductors, 74HCT4067DB,112 Datasheet

IC MUX/DEMUX 1X16 24SSOP

74HCT4067DB,112

Manufacturer Part Number
74HCT4067DB,112
Description
IC MUX/DEMUX 1X16 24SSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT4067DB,112

Function
Multiplexer/Demultiplexer
Circuit
1 x 1:16
On-state Resistance
60 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
4.5 V ~ 5.5 V
Current - Supply
50µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2861-5
935190030112
1. General description
2. Features
3. Applications
The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the other side
connected to a common input/output (Z).
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low
impedance ON-state). All unselected switches are in the high-impedance OFF-state.
With pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins
S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between V
and GND as a negative limit. V
I
I
I
I
I
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Rev. 03 — 15 October 2007
Low ON resistance:
Typical ‘break before make’ built-in
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
N
N
N
80
70
60
(typical) at V
(typical) at V
(typical) at V
CC
CC
CC
= 4.5 V
= 6.0 V
= 9.0 V
CC
to GND may not exceed 10 V.
Product data sheet
CC
as a positive limit

Related parts for 74HCT4067DB,112

74HCT4067DB,112 Summary of contents

Page 1

Rev. 03 — 15 October 2007 1. General description The 74HC4067; 74HCT4067 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4067B. The device is specified in compliance with JEDEC standard no. ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC4067 74HC4067N +125 C 74HC4067D +125 C 74HC4067DB +125 C 74HC4067PW +125 C 74HC4067BQ +125 C 74HCT4067 74HCT4067N +125 C 74HCT4067D +125 C 74HCT4067DB +125 C 74HCT4067PW +125 C 74HCT4067BQ +125 C 74HC_HCT4067_3 Product data sheet 74HC4067; 74HCT4067 ...

Page 3

... NXP Semiconductors 5. Functional diagram 001aag725 Fig 1. Logic symbol Fig 3. Schematic diagram (one switch) 74HC_HCT4067_3 Product data sheet Y10 21 Y11 20 Y12 19 Y13 18 Y14 17 Y15 16 Fig 2. IEC logic symbol V CC GND from logic Rev. 03 — 15 October 2007 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer G16 ...

Page 4

... NXP Semiconductors Fig 4. Functional diagram 74HC_HCT4067_3 Product data sheet 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer 1-OF-16 DECODER E 15 001aag727 Rev. 03 — 15 October 2007 Y10 20 Y11 19 Y12 18 Y13 17 Y14 16 Y15 1 Z © NXP B.V. 2007. All rights reserved ...

Page 5

... NXP Semiconductors Fig 5. Logic diagram 74HC_HCT4067_3 Product data sheet 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer Rev. 03 — 15 October 2007 Y10 Y11 Y12 Y13 Y14 Y15 Z 001aag728 © NXP B.V. 2007. All rights reserved ...

Page 6

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4067 74HCT4067 GND 001aag730 Fig 6. Pin configuration for DIP24, SO24, SSOP24 and TSSOP24 6.2 Pin description Table 2. Pin description Symbol Pin Description Z 1 common input/output Y7 2 independent input/output independent input/output independent input/output independent input/output 4 ...

Page 7

... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Description E 15 enable input (active LOW) Y15 16 independent input/output 15 Y14 17 independent input/output 14 Y13 18 independent input/output 13 Y12 19 independent input/output 12 Y11 20 independent input/output 11 Y10 21 independent input/output independent input/output independent input/output supply voltage CC 7. Functional description [1] Table 3 ...

Page 8

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I switch clamping current SK I switch current SW I supply current CC I ground current ...

Page 9

... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter 74HCT4067 V supply voltage CC V input voltage I V switch voltage SW t rise time r t fall time f T ambient temperature amb 10. Static characteristics Table 6. R resistance per switch for types 74HC4067 and 74HCT4067 for test circuit see ...

Page 10

... NXP Semiconductors GND GND ---------- - Fig 8. Test circuit for measuring R Table 7. Static characteristics 74HC4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter amb ...

Page 11

... NXP Semiconductors Table 7. Static characteristics 74HC4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter I supply current CC C input capacitance +85 C amb V HIGH-level input voltage ...

Page 12

... NXP Semiconductors Table 7. Static characteristics 74HC4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter I OFF-state leakage current S(OFF) I ON-state leakage current S(ON) ...

Page 13

... NXP Semiconductors Table 8. Static characteristics 74HCT4067 At recommended operating conditions; voltages are referenced to GND (ground = 0 V the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter I ON-state leakage current S(ON) I supply current CC I additional supply current ...

Page 14

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics 74HC4067 GND = ns unless specified otherwise; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter t propagation delay pd t turn-off time off ...

Page 15

... NXP Semiconductors Table 9. Dynamic characteristics 74HC4067 GND = ns unless specified otherwise; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter t turn-on time on C power dissipation PD capacitance [ the same as t and t ...

Page 16

... NXP Semiconductors Table 10. Dynamic characteristics 74HCT4067 GND = ns unless specified otherwise; for test circuit see the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter Conditions t propagation delay see turn-off time E to Yn; see ...

Page 17

... NXP Semiconductors 12. Waveforms Fig 12. Input ( output ( inputs V output os V output os Measurement points are shown in Fig 13. Turn-on and turn-off times Table 11. Measurement points Type 74HC4067 74HCT4067 74HC_HCT4067_3 Product data sheet input is t PLH output os ) propagation delays PLZ PHZ 90 % switch ON switch OFF Table 11 ...

Page 18

... NXP Semiconductors GENERATOR Test data is given in Table 12. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch. Fig 14. Load circuitry for measuring switching times Table 12. Test data Test Input ...

Page 19

... NXP Semiconductors 13. Additional dynamic characteristics Table 13. Additional dynamic characteristics Recommended conditions and typical values; GND = the input voltage terminal, whichever is assigned as an input the output voltage terminal, whichever is assigned as an output. os Symbol Parameter THD total harmonic distortion isolation (OFF-state) iso frequency response ...

Page 20

... NXP Semiconductors (dB) a. Isolation (OFF-state) b. Test circuit Fig 16. Isolation (OFF-state function of frequency 74HC_HCT4067_3 Product data sheet 0 iso 100 0 4.5 V; GND = Rev. 03 — 15 October 2007 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer GND 001aag737 = source 001aae332 6 10 (kHz) © NXP B.V. 2007. All rights reserved. ...

Page 21

... NXP Semiconductors V (dB) a. Typical 3 dB frequency response b. Test circuit Fig 17 frequency response 74HC_HCT4067_3 Product data sheet 0 4.5 V; GND = Rev. 03 — 15 October 2007 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer GND 001aag738 = source 001aag739 6 10 (kHz) © NXP B.V. 2007. All rights reserved ...

Page 22

... NXP Semiconductors 14. Package outline DIP24: plastic dual in-line package; 24 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 5.1 0.51 4 inches 0.2 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 23

... NXP Semiconductors SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 24

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 20. Package outline SOT340-1 (SSOP24) ...

Page 25

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 26

... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 27

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added: type numbers 74HC4067BQ and 74HCT4067BQ (DHVQFN24 package). ...

Page 28

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 29

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 14 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 Additional dynamic characteristics . . . . . . . . 19 14 Package outline ...

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