NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet

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NOIL1SM0300A-QDC

Manufacturer Part Number
NOIL1SM0300A-QDC
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of NOIL1SM0300A-QDC

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NOIL1SM0300A
LUPA300 CMOS Image
Sensor
Features
Applications
Overview
6.3 mm x 4.7 mm optical active area (1/2 inch).
resolution, where integration during readout is possible. The readout speed can be boosted by means of subsampling and
windowed Region Of Interest (ROI) readout. High dynamic range scenes can be captured using the double and multiple slope
functionality. User programmable row and column start/stop positions allow windowing. subsampling reduces resolution
while maintaining the constant field of view and an increased frame rate. The programmable gain and offset amplifier maps
the signal swing to the ADC input range. A 10-bit ADC converts the analog data to a 10-bit digital word stream. The sensor
uses a 3-wire Serial-Parallel (SPI) interface. It operates with a 3.3 V and 2.5 V power supply and requires only one master
clock for operation up to 80 MHz pixel rate. It is housed in an 48-pin ceramic LCC package.
NOTE: For more information, see Ordering Code Information on page 27.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. 9
NOIL1SM0300A-QDC
NOIL1SE0300A-QDC
NOIL1SM0300A-WWC
ORDERING INFORMATION
This document describes the interfacing and driving of the LUPA300 image sensor. The pixel size and resolution result in a
This VGA-resolution CMOS active pixel sensor features global shutter and a maximal frame rate of 250 fps in full
The sensor is available in a monochrome version or Bayer (RGB) patterned color filter array.
This data sheet allows the user to develop a camera-system based on the described timing and interfacing.
Active Pixel Sensor Technology of FillFactory (US patent No.
6,225,670 and others)).
These Devices are Pb−Free and are RoHS Compliant
640(H) x 480(V) Active Pixels (VGA Resolution)
9.9 mm x 9.9 mm Square Pixels (Based on the High-Fill Factor
Optical Format: 1/2 Optical Inch
Pixel Rate of 80 MHz
Frame Rate: 250 fps at Full Resolution
On-Chip 10 bit ADCs
Global Shutter
subsampling (Y Direction)
Serial Pheripheral Interface (SPI)
Programmable Read Out Direction (X and Y)
Random Programmable Windowing
Power Dissipation: 190 mW
48-pin LCC Package
Machine Vision
Motion Tracking
Marketing Part Number
Mono with Glass
Color micro lens with Glass
Mono Wafer Sales
1
Description
Figure 1. LUPA300 Package Photo
http://onsemi.com
Publication Order Number:
Wafer Sales
48 pin LCC
Package
NOIL1SM0300A/D

Related parts for NOIL1SM0300A-QDC

NOIL1SM0300A-QDC Summary of contents

Page 1

... The sensor is available in a monochrome version or Bayer (RGB) patterned color filter array. This data sheet allows the user to develop a camera-system based on the described timing and interfacing. ORDERING INFORMATION Marketing Part Number NOIL1SM0300A-QDC NOIL1SE0300A-QDC NOIL1SM0300A-WWC NOTE: For more information, see Ordering Code Information on page 27. ...

Page 2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . ...

Page 3

... This device does NOT contain circuitry to protect the inputs against damage caused by high static voltages or electric fields. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer to Application Note AN52561. 4. The LUPA300 does not have latchup protection. ...

Page 4

Spectral Response Curve 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 400 500 Photo−voltaic Response Curve 1.2 1 0.8 0.6 0.4 0.2 0 0.00E+00 1.00E+04 2.00E+04 600 700 Wavelength (nm) Figure 2. Spectral Response of LUPA300 3.00E+04 4.00E+04 electrons ...

Page 5

The floor plan of the architecture is shown in Figure 4. The image core consists of a pixel array and Y-addressing register, pixel array drivers, and column amplifiers. The image sensor of 640 x 480 pixels is read ...

Page 6

Frame Rate and Windowing Frame Rate The frame rate depends on the input clock, the Frame Overhead Time (FOT) and the Row Overhead Time (ROT). The frame period is calculated as follows Frame period = FOT + Nr. Lines * ...

Page 7

CLK_ADC ADC_IN D1 D2 ADC_OUT <9:0> Programmable Gain Amplifiers The programmable gain amplifiers have two functions: • Adding an offset to the signal to fit it into the range of the ADC. This is controlled by the VBLACK and ...

Page 8

Programmable Gain The amplification inside the PGA is controlled by three SPI settings: The PGA gain selection: 16 gain steps are selectable by means of the GAIN_PGA<3:0> register. Selection word 0000 corresponds with gain 1.32 and selection word 1111 corresponds ...

Page 9

Operation and Signaling Power Supplies Every module on chip such as column amplifiers, output stages, digital modules, and drivers has its own power supply and ground. Off chip the grounds can be combined, but not all power supplies may be ...

Page 10

Biasing Table 9 summarizes the biasing signals required to drive this image sensor. For optimization reasons of the biasing of Table 9. OVERVIEW OF BIAS SIGNALS [1] Signal ADC_BIAS Connect with PRECHARGE_BIAS Connect with 68 kW ...

Page 11

Global Shutter In a global shutter light integration takes place on all pixels in parallel, although subsequent readout is sequential. Figure 10 shows the integration and read out sequence for the synchronous shutter. All pixels are light sensitive at the ...

Page 12

Table 11. ADVANTAGES AND DISADVANTAGES OF NON DESTRUCTIVE READOUT Advantages Low noise because true CDS. High sensitivity because the conversion capacitance is kept rather low. High dynamic range because the results includes signal for short and long ...

Page 13

Table 12. INTERNAL REGISTERS Address 9 (1001) 7:0 10 (1010) 7:0 11 (1011) 11 (1100) 11 (1101) 11:0 14 (1110) 11:0 15 (1111) 8:0 Detailed Description of the Internal ...

Page 14

Res2_enable (1bit) This bit enables/disables the dual slope mode of the device. 1: Dual slope is enabled (configured according to the RES2_TIMER register) 0: Dual slope is disabled (RES2_timer register is ignored) - default Res3_enable (1bit) This bit enables/disables the ...

Page 15

Voffset <7:0> This register is the input for the on-chip DAC, which generates the Voffset supply used by the PGA. When the register is ”00000000” it sets a Voffset of 2.5V. When the register is 11111111 then it sets a ...

Page 16

Calibration Word <32:0> The calibration word for the ADCs is distributed over three registers (13, 14 and 15). These registers all have their default value and changing this value is not recommended. The default register values are: calib_adc<11:0>: 101011011111 ...

Page 17

TIMING AND READOUT OF THE IMAGE SENSOR The timing of the sensor consists of two parts. The first part is related with the integration time and the control of the pixel. The second part is related to the readout of ...

Page 18

RESET_N RESET PIXEL PIXEL SAMPLE # LINES READOUT The line counter starts with the value 1 immediately after the rising edge of RESET_N and after the end of the FOT. This means that the four integration timing registers must be ...

Page 19

Readout Time Smaller Than or Equal to Integration Time In this situation the RES_LENGTH register can be uploaded with the smallest possible value, this is the value ’2’. The frame rate is determined by the integration time. The readout time ...

Page 20

RESET_N SPI INT_TIME_1 INT_TIME_2 INT_TIME_3 RESET (internal) DS RESET (internal) TS RESET (internal) PIXEL SAMPLE (internal) FOT Readout Timing The sensor is readout row by row. The LINE_VALID signal shows when valid data of a row is at the outputs. ...

Page 21

The data at the output of the sensor is clocked on the rising edge of CLK. There is a delay of 3.2 ns between the rising edge of CLK and a change in DATA<9:0>. After this delay DATA<9:0> needs 6 ...

Page 22

Startup Timing On startup, VDDD should rise together with or before the other supplies. The rise of VDDD should be limited to 1V/100 ms to avoid activation of the on chip ESD protection circuitry. During the rise of VDDD an ...

Page 23

Table 14. PINLIST Pin No. Name 1 GND ADC 2 DATA<5> 3 DATA<6> 4 DATA<7> 5 DATA<8> 6 DATA<9> 7 GND DDD 9 GND ADC 10 V ADC 11 GND DDA 13 ADC_BIAS 14 ...

Page 24

Table 14. PINLIST Pin No. Name 34 GND DDA 36 GND A 37 RESET_N 38 CLK 39 V ADC 40 GND ADC 41 V DDO 42 GND O 43 DATA<0> 44 DATA<1> 45 DATA<2> 46 DATA<3> 47 ...

Page 25

PACKAGE DRAWING Figure 25. Package Drawing (001−45394) http://onsemi.com 25 ...

Page 26

Mechanical Package Specification Mechanical Specifications Die Die thickness (with Pin 1 Die center, X offset to the center of the package to the left center) Die center, Y offset to the center of the package Die position, X tilt Die ...

Page 27

... Figure 26 shows the transmission characteristics of the glass lid. Figure 26. Transmission Characteristics of the Glass Lid For proper handling and storage conditions, refer to the ON Semiconductor application note AN52561. ON Semiconductor’s Image Sensor Business Unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to Seller’ ...

Page 28

Acronym Description ADC analog-to-digital converter AFE analog front end BL black pixel data CDM Charged Device Model CDS correlated double sampling CMOS complementary metal oxide semiconductor CRC cyclic redundancy check DAC digital-to-analog converter DDR double data rate DFT design for ...

Page 29

A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. Con- version gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is ...

Page 30

... N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 30 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NOIL1SM0300A/D ...

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