NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 17

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

part is related with the integration time and the control of the
pixel. The second part is related to the readout of the image
sensor. Integration and readout can be in parallel. In this
case, the integration time of frame I is ongoing during
readout of frame I-1. Figure 14 shows this parallel timing
structure.
Time (FOT) during which the analog value on the pixel
diode is transferred to the pixel memory element. After this
FOT, the sensor is read out line per line. The readout of every
line starts with a Row Overhead Time (ROT) during which
Integration Timing in Mastermode
integration time, and triple slope (TS) integration time are
set by the SPI settings. Figure 15 shows the integration
timing and the relationship with the SPI registers. The
timing concerning integration is expressed in number of
lines read out. The timing is controlled by four SPI registers
which need to be uploaded with the desired number of lines.
This number is then compared with the line counter that
keeps track of the number of lines that is read out.
(minus 1) after which the pixel reset drops and the
integration starts.
The timing of the sensor consists of two parts. The first
The readout of every frame starts with a Frame Overhead
In mastermode the integration time, the dual slope (DS)
RES1_LENGTH <11:0>: The number of lines read out
FOT
ROT
Integration frame I+1
Readout frame I
L1
TIMING AND READOUT OF THE IMAGE SENSOR
K1
Figure 14. Global Readout Timing
L2
K2
Readout Pixels
Readout Lines
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the pixel value is put on the column lines. Then the pixels are
selected in groups of 4. So in total 160 kernels of 4 pixels are
read out. The internal timing is generated by the sequencer.
The sequencer can operate in 2 modes: master mode and
slave mode. In master mode all the internal timing is
controlled by the sequencer, based on the SPI settings. In
slave mode the integration timing is directly controlled over
three pins, the readout timing is still controlled by the
sequencer. The selection between master and slave mode is
done by the MASTERMODE register of the SPI. The
sequencer is clocked on the core clock; this is the same clock
as the ADCs. The core clock is the input clock divided by 4.
(minus 1) after which the dual slope reset pulse is given. The
length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
(minus 1) after which the triple slope reset pulse is given.
The length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
1) after which the Frame Transfer (FT) and the FOT starts.
The length of the pulse is given by the formula:
4*(12*(GRAN<1:0>+1)+1) (in clock cycles).
RES2_TIMER <11:0>: The number of lines read out
RES3_TIMER < 11:0>: The number of lines read out
FT_TIMER <11:0>: The number of lines read out (minus
Integration frame I+2
Readout frame I+1
L480
K160