NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 18

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

the rising edge of RESET_N and after the end of the FOT.
This means that the four integration timing registers must be
uploaded with the desired number of lines plus one.
steps of two. In this mode, the counter starts with the value
‘2’ immediately with the rising edge of RESET_N. This
means that for correct operation, the four integration timing
registers can only be uploaded with an even number of lines
if subsampling is enabled.
The line counter starts with the value 1 immediately after
In subsampling mode, the line counter increases with
RESET_N
READOUT
SAMPLE
RESET
# LINES
PIXEL
PIXEL
INT_TIME1
INT_TIME2
INT_TIME3
(internal )
RESET_N
RESET
RESET
Transfer
RESET
Frame
DS
TS
Figure 15. Integration Timing in Master Mode
1
Res1_length
Figure 16. INT_TIME Timing
http://onsemi.com
Res2_timer
18
and the TS integration time are indicated by 3 output pins:
INT_TIME_1, INT_TIME_2 and INT_TIME_3. These
outputs are high during the actual integration time. This is
from the falling edge of the corresponding reset pulse to the
falling edge of the internal pixel sample. Figure 16 illustrates
this. The internal pixel sample rises at the moment defined
by FT_TIMER (see Figure 15) and the length of the pulse is
4*(12*(GRAN<1:0>+1)+2).
The length of the integration time, the DS integration time
Res3_timer
Total
Integration Time
DS Integration Time
FT_timer
FOT
TS
Time
Integration
1
Res1_length