NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 13

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Detailed Description of the Internal Registers
frame valid is low).
is low:
•
•
Sequencer Register <10:0>
controls all of the sequencer settings. It contains several
”sub-registers”.
Mastermode (1 bit)
The sequencer can operate in two modes: master mode and
slave mode. In master mode all the internal timing is
controlled by the sequencer, based on the SPI settings. In
slave mode the integration timing is directly controlled over
three pins, the readout timing is still controlled by the
sequencer.
Subsampling (1bit)
Subsampling is only possible in Y direction and follows this
pattern:
Table 12. INTERNAL REGISTERS
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
The registers should only be changed during FOT (when
These registers should only be changed during RESET_N
The sequencer register is an 11 bit wide register that
This bit controls the selection of mastermode/slavemode.
1: Master mode (default)
0: Slave mode
This bit enables/disables the subsampling mode.
Mastermode register
Granularity register
Address
7:0
7:0
11:0
4
4
4
11:0
4
1
1
1
4
1
11:0
11:0
8:0
Bits
VBLACK
VOFFSET
ANA_IN_ADC
sel_test_path
sel_path
bypass_mux
PGA_SETTING
gain_pga
unity_pga
sel_uni
enable_analog_in
enable_adc
sel_calib_fast
CALIB_ADC <11:0>
CALIB_ADC <23:12>
CALIB_ADC <32:24>
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Name
•
Clock granularity (2 bits)
chip.
shutter sequencer, can be programmed using the granularity
register. The value of this register depends on the speed of
your system clock.
Enable analog out (1 bit)
Calib_line (1bit)
calibration modes can be set, at the beginning of the frame
and for every subsequent line that is read.
noise)
By default, the subsampling mode is disabled.
The system clock (80 MHz) is divided several times on
The clock, that drives the ”snapshot” or synchronous
11: > 80 MHz
10: 40-80 MHz (default)
01: 20-40 MHz
00: < 20 MHz
This bit enables/disables the analog output amplifier.
1: enabled
0: disabled (default)
This bit sets the calibration method of the PGA. Different
1: Calibration is done every line (default)
0: Calibration is done every frame (less row fixed pattern
Read one, skip one: Y0Y0Y0Y0…
DAC input for vblack
Default <7:0>: 01101011
DAC input for voffset
Default <7:0>: 01010101
Activate analog ADC input
Default <11:0>: 000011110000
Selection of analog test path
Selection of normal analog path
Bypass of digital 4 to 1 mux
PGA settings
Default <11:0>: 111110110000
Gain settings PGA
PGA unity amplification
Preamplification of 0.5 (0: enabled)
Activate analog input
Put separate ADCs in standby
Select fast calibration of PGA
Calibration word of the ADCs
Default:
calib_adc<11:0>:101011011111
calib_adc<23:12>:011011011011
calib_adc<32:24>:000011011011
Description