DP83848IVV National Semiconductor, DP83848IVV Datasheet - Page 51

• Manufacturer Part Number: DP83848IVV
• Manufacturer: National Semiconductor

Specifications of DP83848IVV

• Lead Free Status / Rohs Status: Compliant

Bit
5
4
3
2
1
0
Auto-Neg Complete
Loopback Status
Jabber Detect
Duplex Status
Speed Status
Link Status
Bit Name
Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued)
Default
0, RO
0, RO
0, RO
0, RO
0, RO
0, RO
Jabber Detect: This bit only has meaning in 10 Mb/s mode
This bit is a duplicate of the Jabber Detect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
Loopback:
1 = Loopback enabled.
0 = Normal operation.
Duplex:
This bit indicates duplex status and is determined from Auto-Nego-
tiation or Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and com-
plete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
Speed10:
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and com-
plete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register,
except that it will not be cleared upon a read of the PHYSTS regis-
ter.
1 = Valid link established (for either 10 or 100 Mb/s operation)
0 = Link not established.
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Description
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