DP83848IVV National Semiconductor, DP83848IVV Datasheet - Page 68
DP83848IVV
Manufacturer Part Number
DP83848IVV
Description
Manufacturer
National Semiconductor
Datasheet
1.DP83848IVV.pdf
(84 pages)
Specifications of DP83848IVV
Lead Free Status / Rohs Status
Compliant
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8.2.7 100BASE-TX Transmit Packet Deassertion Timing
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser-
tion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
T2.7.1
Parameter
PMD Output Pair
TX_CLK to PMD Output Pair
Deassertion
TX_CLK
TX_EN
TXD
Description
DATA
DATA
100 Mb/s Normal mode
T2.7.1
68
Notes
(T/R)
(T/R)
IDLE
IDLE
Min
Typ
6
Max
Units
bits
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