M45PE10-VMN6TP Micron Technology Inc, M45PE10-VMN6TP Datasheet - Page 32

• Manufacturer Part Number: M45PE10-VMN6TP
• Manufacturer: Micron Technology Inc

Specifications of M45PE10-VMN6TP

• Cell Type: NOR
• Density: 1Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC N
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

Power-up and power-down
7
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Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold value, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),
page erase (PE) and sector erase (SE) instructions until a time delay of t
after the moment that V
the device is not guaranteed if, by this time, V
erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for read instructions even if the t
As an extra protection, the Reset (Reset) signal can be driven Low for the whole duration of
the power-up and power-down phases.
At power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V
(POR) threshold value, V
any instruction (the designer needs to be aware that if a power-down occurs while a write,
program or erase cycle is in progress, some data corruption can result).
V
V
t
t
The device is in the standby power mode (not the deep power-down mode)
The write enable latch (WEL) bit is reset
The write in progress (WIP) bit is reset
PUW
VSL
CC
SS
(min) at power-up, and then for a further delay of t
at power-down
after wrap round V
after V
VSL
, has elapsed, after V
CC
passed the V
CC
CC
WI
rises above the V
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond to
CC
Table
CC
passed the V
) until V
WI
Section 3: SPI
6.
threshold
CC
WI
has risen above V
CC
PUW
CC
– all operations are disabled, and the device
reaches the correct value:
WI
CC
CC
line decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
threshold. However, the correct operation of
(min) level
is still below V
modes.
VSL
CC
(min), the device can be
CC
(min). No write, program or
CC
PUW
is less than the
has elapsed
CC
supply.
M45PE10