LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 3

• Manufacturer Part Number: LAXP2-17E-5QN208E
• Description: IC FPGA AUTO 17K LUTS 208-PQFP
• Manufacturer: Lattice

Specifications of LAXP2-17E-5QN208E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Introduction
Lattice Semiconductor
LA-LatticeXP2 Family Data Sheet
Introduction
LA-LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an archi-
tecture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LA-LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and
low cost in mind. LA-LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase
Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
®
The ispLEVER
design tool from Lattice allows large and complex designs to be efficiently implemented using the
LA-LatticeXP2 family of FPGA devices. Synthesis library support for LA-LatticeXP2 is available for popular logic
synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning
tools to place and route the design in the LA-LatticeXP2 device. The ispLEVER tool extracts the timing from the
routing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORE™ modules for the LA-LatticeXP2
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
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