AFBR-5972Z Avago Technologies US Inc., AFBR-5972Z Datasheet - Page 2

• Manufacturer Part Number: AFBR-5972Z
• Description: 51T5233
• Manufacturer: Avago Technologies US Inc.

Specifications of AFBR-5972Z

• Applications: Fast Ethernet
• Data Rate Max: 100Mbps
• Supply Voltage: 3.3V
• Wavelength Typ: 650nm
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Product: Transceiver
• Data Rate: 125 MBd
• Wavelength: 650 nm
• Maximum Rise Time: 3.5 ns
• Maximum Fall Time: 3.5 ns
• Pulse Width Distortion: 1 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Maximum Forward Current: 120 mA
• Maximum Power Dissipation: 436 mW
• Transmission Distance: 50 m, 70 m
• Lead Free Status / Rohs Status: Details
• For Use With: AFBR-4526Z

Figure 2. PCB footprint and Pin-out diagram.
The opto-electrical subassemblies utilize a high volume
assembly process together with low cost lens elements
which result in a cost eff ective building block. It consists
of the active III-V devices, IC chips and various surface
mounted passive components.
There are eight signal pins, four EMI shield solder posts
and two mounting posts, which exit the bottom of the
housing. The solder posts are isolated from the internal
circuit of the transceiver and are to be connected to chas-
sis ground. The mounting posts are to provide mechanical
strength to hold the transceiver to the application board.
Pin Descriptions
Pin 1 TData+: transmitter data in. This input is a 3.3V LVPE-
CL/LVDS compatible diff erential line.
Pin 2 TData-: transmitter data in negative. This input is a
3.3V LVPECL/LVDS compatible diff erential line.
Pin 3 TX Vcc: transmitter power supply pin. Provide +3.3
V DC via a transmitter power supply fi lter circuit. Locate
the power supply fi lter circuit as close as possible to the
Tx Vcc pin.
2
8.89
6.35
3.05
T op View
∅
3.2
0
+
0.1
(2x)
1
2
3
4
F ront
5
6
7
8
S T ANDOF F
AR E A (2 x 0.65 x 1.03)
8.66
3.18
0
3.73
S T ANDOF F
AR E A (4 x 1.9 x 1)
Pin 4 GND: common ground pin. Directly connect this pin
to the signal ground plane of the host board.
Pin 5 RX Vcc: receiver power supply pin. Provide +3.3 V DC
via a receiver power supply fi lter circuit. Locate the power
supply fi lter circuit as close as possible to the Rx Vcc pin
Pin 6. SD: signal detect pin. If an optical signal is present
at the optical input, SD output is a logic “1”. Absence of an
optical input signal results in a logic “0” output. This pin
can be used to drive a LVPECL input of an upstream circuit,
such as Signal Detect input or Loss of Signal–bar.
Pin 7 RData+: receiver data out. This data line is a 3.3V
LVPECL compatible diff erential line which should be prop-
erly terminated.
Pin 8 RData-: receiver data out negative. This data line is a
3.3V LVPECL compatible diff erential line which should be
properly terminated. When SD is de-asserted, RData+ will
be set to logic “0” and RData- will be set to logic “1”.
Shield: This is to be connected to the equipment chassis
ground.
UNP LAT E D (2x)
MOUNT P OS T
NOT E S :
1) Dimens ion: mm
2) G eneral tolerance: ± 0.05
3) R ecommended P C B Thickness 1.57
4) P in des cription
P IN
1
2
3
4
5
6
7
8
F UNC
T D+
T D-
T xV cc
G ND
R xVcc
S D
R D+
R D-
± 0.05