MT48LC4M16A2P-75:GTR Micron Technology Inc, MT48LC4M16A2P-75:GTR Datasheet - Page 27

• Manufacturer Part Number: MT48LC4M16A2P-75:GTR
• Manufacturer: Micron Technology Inc

Specifications of MT48LC4M16A2P-75:GTR

• Lead Free Status / Rohs Status: Compliant

Figure 14:
Figure 15:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
READ-to-WRITE
READ-to-WRITE With Extra Clock Cycle
Note:
Note:
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 14
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 15 shows the case where the additional NOP is
needed.
COMMAND
COMMAND
ADDRESS
ADDRESS
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of one is used, then DQM is not required.
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
COL n
T0
BANK,
T0
COL n
READ
READ
TRANSITIONING DATA
T1
T1
NOP
NOP
27
T2
T2
TRANSITIONING DATA
NOP
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
t HZ
OUT
t HZ
D
t CK
OUT
n
n
DON’T CARE
T4
BANK,
T4
COL b
WRITE
NOP
D
IN
b
t
DS
64Mb: x4, x8, x16 SDRAM
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS
©2000 Micron Technology, Inc. All rights reserved.
Commands