MT48LC32M16A2P-75:CTR Micron Technology Inc, MT48LC32M16A2P-75:CTR Datasheet

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MT48LC32M16A2P-75:CTR

Manufacturer Part Number
MT48LC32M16A2P-75:CTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC32M16A2P-75:CTR

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Synchronous DRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
Table 1:
Table 2:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAMfront.fm - Rev. L 10/07 EN
Configuration 32 Meg x 4
Refresh count
Row
addressing
Bank
addressing
Column
addressing
Speed
Grade
Parameter
edge of system clock
changed every clock cycle
and auto refresh modes
-7E
-75
-7E
-75
Frequency
100 MHz
143 MHz
133 MHz
133 MHz
MT48LC32M16A2P-75:C
Clock
Address Table
Key Timing Parameters
Products and specifications discussed herein are subject to change by Micron without notice.
8K (A0–A12) 8K (A0–A12)
4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
32 Meg x 4 32 Meg x 8 32 Meg x 16
4K (A0–A9,
Part Number Example:
A11, A12)
x 4 banks
8K
CL = 2 CL = 3
5.4ns
Access Time
6ns
16 Meg x 8
2K (A0–A9,
x 4 banks
5.4ns
5.4ns
A11)
8K
Setup
Time
1.5ns
1.5ns
1.5ns
1.5ns
8K (A0–A12)
1K (A0–A9)
8 Meg x 16
x 4 banks
8K
Hold
Time
0.8ns
0.8ns
0.8ns
0.8ns
1
Notes: 1. Refer to Micron technical note: TN-48-05.
Options
• Configurations
• WRITE recovery (
• Plastic package – OCPL
• Timing (cycle time)
• Self refresh
• Operating temperature range
• Revision
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free
– 7.5ns @ CL = 2 (PC133)
– 7.5ns@ CL = 3 (PC133)
– Standard
– Low power
– Commercial (0
– Industrial (–40
t
WR = “2 CLK”
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2. Off-center parting line.
3. Contact factory for availability.
4. Available on x4 and x8 only.
1
o
o
t
512Mb: x4, x8, x16 SDRAM
C +85
C to +70
WR)
2
o
C)
o
©2000 Micron Technology, Inc. All rights reserved.
C)
Marking
Features
128M4
32M16
64M8
None
None
-7E
-75
TG
A2
L
IT
:C
P
3
4

Related parts for MT48LC32M16A2P-75:CTR

MT48LC32M16A2P-75:CTR Summary of contents

Page 1

... MHz 5.4ns -75 100 MHz 6ns Part Number Example: MT48LC32M16A2P-75:C PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMfront.fm - Rev. L 10/07 EN Products and specifications discussed herein are subject to change by Micron without notice. Options • Configurations – 128 Meg x 4 (32 Meg banks) – 64 Meg x 8 (16 Meg banks) – ...

Page 2

... Electrical Specifications .42 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timing Diagrams .49 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMTOC.fm - Rev. L 10/07 EN 512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2000 Micron Technology, Inc. All rights reserved. Table of Contents ...

Page 3

... List of Figures Figure 1: 128 Meg x 4 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 2: 64 Meg x 8 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3: 32 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 5: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 7: Activating a Specific Row In a Specific Bank ...

Page 4

... Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DD Table 15: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 16: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .45 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAMLOT.fm - Rev. L 10/07 EN 512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2000 Micron Technology, Inc. All rights reserved. List of Tables ...

Page 5

... A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths (BL locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...

Page 6

... Figure 1: 128 Meg x 4 SDRAM Functional Block Diagram CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ BANK0 ROW- 13 ROW- ADDRESS ADDRESS MUX MEMORY 8192 LATCH & (8,192 x 4,096 x 4) ...

Page 7

... Figure 2: 64 Meg x 8 SDRAM Functional Block Diagram CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ BANK0 ROW- 13 ROW- ADDRESS ADDRESS MUX MEMORY 8192 LATCH & (8,192 x 2,048 x 8) ...

Page 8

... Figure 3: 32 Meg x 16 SDRAM Functional Block Diagram CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 13 A0–A12, ADDRESS 15 BA0, BA1 REGISTER PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ BANK0 ROW- 13 ROW- ADDRESS ADDRESS MUX MEMORY 8192 LATCH & (8,192 x 1,024 x 16) ...

Page 9

... Pin Assignment (Top View) 54-Pin TSOP DQ0 - DQ1 - Note: The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is same as x16 pin function. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ x16 - DQ0 DQ0 DQ1 4 DQ1 DQ2 5 - VssQ 6 NC DQ3 7 DQ2 DQ4 ...

Page 10

... SS PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...

Page 11

... Functional Description The 512Mb SDRAMs (32 Meg banks, 16 Meg banks, and 8 Meg banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’ ...

Page 12

... Issue an AUTO REFRESH command. 11. Wait at least are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register ...

Page 13

... Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of BL, a burst type, CL, an operating mode, and a write burst mode, as shown in Figure 5 on page 14. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0– ...

Page 14

... Reserved Write Burst Mode M9 0 Programmed burst length 1 Single location access M8 M7 M6- Defined – – – Notes: 1. Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN A11 A10 Mode CAS Latency ...

Page 15

... For example, assuming that the clock cycle time is such that all relevant access times are met READ command is registered at T0 and the PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN Order of Accesses Within a Burst Starting Column Address Type = Sequential – ...

Page 16

... WRITE Burst Mode When programmed via M0–M2 applies to both READ and WRITE bursts; when the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP ...

Page 17

... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...

Page 18

... Care.” After a bank has been precharged the idle state and must be acti- vated prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ RP) after the PRECHARGE command is issued. Input A10 determines Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 19

... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become “ ...

Page 20

... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...

Page 21

... The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. Figure 9: READ Command A0–A9, A11, A12: x4 A0–A9, A11: x8 A11, A12: x16 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ RCD (MIN) when 2 < RCD (MIN ACTIVE NOP t ...

Page 22

... This is shown in Figure 10 for and data element either the last of a burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...

Page 23

... Figure 11: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK READ NOP NOP NOP BANK, COL n D OUT CLK READ NOP NOP NOP BANK, COL n DQ ...

Page 24

... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...

Page 25

... PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where This is shown in Figure 15 on page 26 for PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK ...

Page 26

... This is shown in Figure 16 on page 27 for each possible CL; data element the last desired data element of a longer burst. Figure 15: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS NOTE: DQM is LOW. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ met. Note that part of the row precharge time CLK READ NOP NOP ...

Page 27

... Figure 16: Terminating a READ Burst COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK READ NOP NOP BANK, COL n D OUT CLK READ NOP NOP BANK, COL 512Mb: x4, x8, x16 SDRAM BURST NOP NOP NOP TERMINATE cycle ...

Page 28

... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 19 on page 29. Data either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture ...

Page 29

... An example is shown in Figure 21 on page 30. Data either the last of a burst of two or the last desired of a longer burst. Figure 19: WRITE-to-WRITE COMMAND ADDRESS Note: DQM is LOW. Each WRITE command may be to any bank. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK WRITE NOP NOP BANK, ...

Page 30

... In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK ...

Page 31

... Figure 22: WRITE-to-PRECHARGE CLK > 15ns COMMAND ADDRESS CLK < 15ns COMMAND ADDRESS Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK DQM WRITE NOP PRECHARGE BANK a, BANK COL n ...

Page 32

... BA0, BA1 are treated as “Don’t Care.” After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Figure 24: PRECHARGE Command A0–A9, A11, A12 PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CLK BURST NEXT ...

Page 33

... Figures 26 and 27 on page 34). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CKS). See Figure 25 ...

Page 34

... In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ ...

Page 35

... Concurrent Auto Precharge An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...

Page 36

... Figure 31 on page 37). Figure 30: WRITE with Auto Precharge Interrupted by a READ CLK COMMAND BANK n Internal States BANK m ADDRESS DQ Note: DQM is LOW. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ - AP NOP NOP NOP BANK n Page READ with Burst of 4 Active Page Active ...

Page 37

... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND MAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...

Page 38

... Table 8 and according to Table 9 on page 40. Row activating: Starts with registration of an ACTIVE command and ends when Read with auto precharge enabled: precharge enabled: PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN WE# Command (Action) X COMMAND INHIBIT (NOP/continue previous operation) H ...

Page 39

... PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN Refreshing: Starts with registration of an AUTO REFRESH command and ends when met. After RC is met, the SDRAM will be in the all banks idle state. Starts with registration of a LOAD MODE REGISTER command and ends t register: when MRD has been met ...

Page 40

... Current state definitions: precharge enabled: Write with auto precharge enabled: 4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN CAS# WE# Command (Action COMMAND INHIBIT (NOP/continue previous operation) ...

Page 41

... WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after istered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 31 on page 37). PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN 512Mb: x4, x8, x16 SDRAM met, where WR begins when the WRITE to bank m is reg- Micron Technology, Inc ...

Page 42

... Micron’s Web site. Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 11 on page 43, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’ ...

Page 43

... Table 12: Summary of Thermal Impedance Die Size Number of 2 (mm ) Package Leads 94 TSOP 54 Figure 32: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN Symbol PEAK , is measured in the center of the package on the top C θ θ JA JMA Test (° ...

Page 44

... Auto refresh current: CS# = HIGH; CKE = HIGH Self refresh current: CKE ≤ 0.2V Table 15: Capacitance Note 2 applies to entire table; notes appear on page 47 Parameter Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQs PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN Symbol ≤ V ...

Page 45

... ACTIVE-to-ACTIVE command period ACTIVE-to-READ or WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN -7E Symbol Min Max AC(3) – t ...

Page 46

... Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN 512Mb: x4, x8, x16 SDRAM Electrical Specifications Symbol -7E t CCD ...

Page 47

... The I frequency is altered for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ dependent on output loading and cycle rates. Specified values are obtained and V Q must be at same potential ...

Page 48

... AC for -75/- with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -75 30. CKE is HIGH during refresh command period limit is actually a nominal value and does not result in a fail value. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ for a pulse width ≤ 3ns, and the pulse width overshoot: V (MAX ...

Page 49

... HIGH at clock high time, all commands applied are NOP. 2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. 5. A12 should be a LOW PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ ...

Page 50

... COMMAND PRECHARGE DQM/ DQML, DQMU A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Note: Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CKS ( ( ) ) ( ( ...

Page 51

... A0–A9, 2 COLUMN m A11, A12 A10 BA0, BA1 BANK DQ Notes: 1. For this example and auto precharge is disabled. 2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CKS t CKH NOP NOP OUT t LZ ...

Page 52

... Auto-Refresh Mode T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ AUTO NOP NOP NOP ( ( REFRESH ...

Page 53

... DQML, DQMU A0–A9, A11,A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes maximum time limit for self refresh XSR requires minimum of two clocks regardless of frequency or timing. PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ CKS t RAS(MIN) ≥ ...

Page 54

... BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP NOP t CMS ...

Page 55

... A10 BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK t AC ...

Page 56

... BANK DQ t RCD t RAS t RC Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP NOP t CMS ...

Page 57

... BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. For this example and x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 3. READ command is not allowed else PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ NOP 3 NOP 3 READ t CMS t CMH ...

Page 58

... BANK RCD - BANK 0 t RAS - BANK BANK 0 t RRD Notes: 1. For this example and x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ...

Page 59

... A11, A12 ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 3. Page left open; no PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP NOP NOP t CMH BANK ...

Page 60

... A10 DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1. For this example and x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ READ NOP NOP t CMS t CMH COLUMN m 2 BANK ...

Page 61

... RC Notes: 1. For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D quency. 3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ WRITE NOP ...

Page 62

... ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1. For this example x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ WRITE NOP NOP NOP t CMH 2 m BANK ...

Page 63

... For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D quency. 3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 4. PRECHARGE command not allowed else PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ ...

Page 64

... For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D quency. 3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” 4. WRITE command not allowed else PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ ...

Page 65

... RRD Notes: 1. For this example Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE. 3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ WRITE NOP ACTIVE ...

Page 66

... A10 BA0, BA1 BANK DQ t RCD Notes: 1. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.” must be satisfied prior to PRECHARGE command. 3. Page left open; no PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ WRITE NOP NOP t CMH t CMS 1 m COLUMN ...

Page 67

... AH ROW A10 BA0, BA1 BANK DQ t RCD Notes: 1. For this example x16: A11 and A12 = “Don’t Care;” x8: A12 = “Don’t Care.” PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/ WRITE NOP NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE ...

Page 68

... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and PDF: 09005aef809bf8f3/Source: 09005aef80818a4a 512MbSDRAM.fm - Rev. L 10/07 EN 0.71 11.76 ±0.20 10.16 ± ...

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