P80C51BH Intel, P80C51BH Datasheet - Page 6

• Manufacturer Part Number: P80C51BH
• Manufacturer: Intel

Specifications of P80C51BH

• Cpu Family: MCS51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Type: ROM
• Program Memory Size: 4KB
• Total Internal Ram Size: 128Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

AUTOMOTIVE 80C31BH 80C51BH 87C51
NOTE
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook and Applica-
tion Note AP-252 ‘‘Designing with the 80C51BH ’’
internal RAM in this event but access to the port
pins is not inhibited To eliminate the possibility of an
unexpected write to a port pin when Idle is terminat-
ed by reset the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory
POWER DOWN MODE
In the Power Down mode the oscillator is stopped
and the instruction that invokes Power Down is the
last instruction executed The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated
The only exit from Power Down is a hardware reset
Reset redefines the SFRs but does not change the
on-chip RAM The reset should not be activated be-
fore V
must be held active long enough to allow the oscilla-
tor to restart and stabilize
6
Idle
Idle
Power Down
Power Down
CC
Mode
is restored to its normal operating level and
Table 2 Status of the External Pins During Idle and Power Down
Program
Memory
External
External
Internal
Internal
ALE
1
1
0
0
PSEN
1
1
0
0
DESIGN CONSIDERATIONS
PORT0
Float
Float
Data
Data
At power on the voltage on V
come up at the same time for a proper start-up
Before entering the Power Down mode the con-
tents of the Carry Bit and B 7 must be equal
When the Idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
in not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
An external oscillator may encounter as much as
a 100 pF load at XTAL1 when it starts up This is
due to interaction between the amplifier and its
feedback capacitance Once the external signal
meets the V
tance will not exceed 20 pF
For EPROM versions exposure to light when the
device is in operation may cause logic errors For
this reason it is suggested that an opaque label
be placed over the window when the die is ex-
posed to ambient light
PORT1
IL
Data
Data
Data
Data
and V
IH
specifications the capaci-
Address
PORT2
Data
Data
Data
CC
and RST must
PORT3
Data
Data
Data
Data