P80C51BH Intel, P80C51BH Datasheet - Page 8

• Manufacturer Part Number: P80C51BH
• Manufacturer: Intel

Specifications of P80C51BH

• Cpu Family: MCS51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Type: ROM
• Program Memory Size: 4KB
• Total Internal Ram Size: 128Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

AUTOMOTIVE 80C31BH 80C51BH 87C51
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias
Storage Temperature
Voltage on EA V
Voltage on Any Other Pin to V
I
Power Dissipation
(Based on package heat transfer limitations not de-
vice power consumption)
Typical Junction Temperature (T
(Based upon ambient temperature at
Typical Thermal Resistance Junction-to-Ambient
(
DC CHARACTERISTICS
(T
NOTES
1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The
values listed are at room temp 5V
2 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations In the worst cases (capacitive loading
exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt
Trigger STROBE input
3 Capacitive loading on Ports 0 and 2 may cause the V
specification when the address bits are stabilizing
8
OL
Symbol
V
V
V
V
V
V
V
V
I
I
I
I
RRST
CIO
IL
TL
LI
CC
IL
IL1
IH
IH1
OL
OL1
OH
OH1
JA
A
per I O pin
)
e b
PDIP
PLCC
40 C to
Input Low Voltage (Except EA)
Input Low Voltage to EA
Input High Voltage (Except XTAL1 RST) 0 2V
Input High Voltage (XTAL1 RST)
Output Low Voltage (Ports 1 2 3)
Output Low Voltage (Port 0 ALE PSEN)
Output High Voltage
(Ports 1 2 3 ALE PSEN)
Output High Voltage (Port 0 in
Logical 0 Input Current (Ports 1 2 3)
Logical 1-to-0 transition current
(Ports 1 2 3)
Input Leakage Current (Port 0)
Power Supply Current
Active Mode
Idle Mode
Power Down Mode
Internal Reset Pulldown Resistor
Pin Capacitance
External Bus Mode)
PP
a
Pin to V
125 C V
12 MHz
Parameter
12 MHz
SS
(5)
CC
SS
(5)
J
e
)
b
b
b
5V
40 C to
65 C to
0 5V to
a
0V to
g
125 C)
10% (5V
a
a
a
a
75 C W
46 C W
a
15 mA
125 C
150 C
135 C
13 0V
0 7 V
1 5W
6 5V
0 9 V
0 9 V
b
Min
CC
2 4
2 4
g
CC
50
0
0 5
OH
20% EPROM Only) V
a
CC
CC
a
1 0
0 1
on ALE and PSEN to momentarily fall below the 0 9 V
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
WARNING Stressing the device beyond the ‘‘Absolute
NOTICE This is a production data sheet The specifi-
cations are subject to change without notice
Typ(1)
11 5
1 3
3
(87C51 80C51BH)
l
0 2 V
0 2 V
100pF) the noise pulse on the ALE pin may
V
V
100 75
CC
CC
0 45
0 45
25 20
b
Max
b
g
CC
CC
6 5
300
10
750
a
a
SS
75
10
b
b
(7)
(7)
0 5
0 5
0 25
0 45
e
0V)
Unit
mA
mA
K
pF
V
V
V
V
V
V
V
V
V
V
A
A
A
A
OL
I
I
I
I
I
I
V
V
V
OL
OL
OH
OH
OH
OH
s of ALE and Ports
IN
IN
CC
e
e
Conditions
e
e
e b
e b
e b
e b
e
1 6 mA
3 2 mA
0 45 V
V
Test
2 2V to 5 5V
IL
(4)
(6)
60 A
10 A
800 A
80 A
or V
(2)
(2)
IH
(3)
CC