SCN2681AC1N28 NXP Semiconductors, SCN2681AC1N28 Datasheet - Page 3

• Manufacturer Part Number: SCN2681AC1N28
• Manufacturer: NXP Semiconductors

Specifications of SCN2681AC1N28

• Number Of Channels: 2
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Through Hole
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
PIN CONFIGURATION
PIN DESCRIPTION
2004 Mar 18
SYMBOL
SYMBOL
D0–D7
CEN
WRN
RDN
A0–A3
RESET
INTRN
Dual asynchronous receiver/transmitter (DUART)
RXDB
TXDB
WRN
GND
OP1
OP3
OP5
OP7
RDN
IP3
IP1
IP0
A0
A1
A2
A3
D1
D3
D5
D7
18
20
10
11
12
13
14
15
16
17
19
1
2
3
4
5
6
7
8
9
1, 2, 3, 4
19, 10,
18, 11,
17, 12,
DIP28
16, 13
26
25
15
5
6
DIP
1, 3, 5, 6
25, 16,
24, 17,
23, 18,
DIP40
22, 19
Pin
35
34
21
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
IP4
IP5
IP6
IP2
CEN
RESET
X2
X1/CLK
RXDA
TXDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
CC
PLCC44
2, 4, 6, 7
28, 18,
27, 19,
26, 20,
25, 21
39
10
38
24
9
TYPE
TYPE
I/O
O
I
I
I
I
I
RXDB
TXDB
WRN
RDN
GND
OP1
D7
D3
A0
A1
A3
D1
D5
A2
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and
status between the DUART and the CPU. D0 is the least significant bit.
Chip Enable: Active-LOW input signal. When LOW, data transfers between the
CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and
A0-A3 inputs. When HIGH, places the D0-D7 lines in the 3-State condition.
Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the
signal.
Read Strobe: When LOW and CEN is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RDN.
Address Inputs: Select the DUART internal registers and ports for read/write
operations.
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR),
puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and
B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state.
Clears Test modes, sets MR pointer to MR1.
Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one
or more of the eight maskable interrupting conditions are true.
Figure 1. Pin configuration
10
11
12
13
14
1
2
3
4
5
6
7
8
9
DIP
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
IP2
CEN
RESET
X2
X1/CLK
RXDA
TXDA
OP0
D0
D2
D4
D6
INTRN
CC
NAME AND FUNCTION
NAME AND FUNCTION
CORNER
INDEX
PIN/FUNCTION
17
7
10 RDN
11 RXDB
12 NC
13 TXDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
1
2
3
4
5
6
7
8
9
18
6
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
TOP VIEW
PLCC
1
PIN/FUNCTION
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TXDA
34 NC
35 RXDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
44 V
SCN2681
40
28
CC
Product data
39
29
SD00723