S87C751-4N24 NXP Semiconductors, S87C751-4N24 Datasheet - Page 19

• Manufacturer Part Number: S87C751-4N24
• Manufacturer: NXP Semiconductors

Specifications of S87C751-4N24

• Cpu Family: 87C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: EPROM
• Program Memory Size: 2KB
• Total Internal Ram Size: 64Byte
• # I/os (max): 19
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

1. Address should be valid at least 24t
2. For a pure verify mode, i.e., no program mode in between, t
Philips Semiconductors
EPROM PROGRAMMING AND VERIFICATION
T
NOTES:
1998 May 01
amb
80C51 8-bit microcontroller family
2K/64 OTP/ROM, I
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
AVGL
GHAX
DVGL
GHDX
SHGL
GHSL
GLGH
AVQV
GHGL
MASEL
HAHLD
HASET
ADSTA
P0.0 (ASEL)
P0.1 (PGM)
P0.2 (V
= 21 C to +27 C, V
CLCL
PORT 3
PORT 1
1
2
PP
)
5V
Oscillator/clock frequency
Address setup to P0.1 (PROG–) low
Address hold after P0.1 (PROG–) high
Data setup to P0.1 (PROG–) low
Data hold after P0.1 (PROG–) high
V
V
P0.1 (PROG–) width
V
P0.1 (PROG–) high to P0.1 (PROG–) low
ASEL high time
Address hold time
Address setup to ASEL
Low address to valid data
t
HASET
PP
PP
PP
setup to P0.1 (PROG–) low
hold after P0.1 (PROG–)
low (V
CC
INVALID DATA
= 5V 10%, V
CC
Purchase of Philips I
to use the components in the I
I
code 9398 393 40011.
HIGH ADDRESS
2
C specifications defined by Philips. This specification can be ordered using the
) to data valid
2
t
MASEL
VERIFY MODE
C, low pin count
CLCL
PARAMETER
SS
before the rising edge of P0.2 (V
= 0V
t
HAHLD
Figure 7. Program/Verify Cycle
t
2
AVGL
LOW ADDRESS
t
ADSTA
C components conveys a license under the Philips’ I
12.75V
VALID DATA
t
GLGH
AVQV
98 s MIN
is 14t
19
2
t
SHGL
C system provided the system conforms to the
CLCL
DATA TO BE PROGRAMMED
PP
t
maximum.
DVGL
).
PROGRAM MODE
10 s + 24t
10 s MIN
25 PULSES
48t
38t
36t
13t
13t
2t
MIN
t
1.2
CLCL
10
10
90
10
GHDX
CLCL
CLCL
CLCL
CLCL
CLCL
t
GHGL
CLCL
INVALID DATA
t
5V
AVQV
t
GHSL
48t
48t
83C751/87C751
MAX
110
VERIFY MODE
CLCL
CLCL
6
2
Product specification
C patent
VALID DATA
UNIT
MHz
SU00303
s
s
s
s