M45PE16-VMW6G Micron Technology Inc, M45PE16-VMW6G Datasheet
M45PE16-VMW6G
Specifications of M45PE16-VMW6G
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M45PE16-VMW6G Summary of contents
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... Deep power-down mode 1 µA (typical) More than 100 000 write cycles More than 20 years data retention Packages – ECOPACK® (RoHS compliant) May 2008 16-Mbit, page-erasable serial flash memory Rev 8 M45PE16 VFQFPN8 (MP) 6 × SO8W (MW) 208 mils body width 1/47 www.numonyx.com 1 ...
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... Active power, standby power and deep power-down modes . . . . . . . . . . 13 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write enable (WREN 6.2 Write disable (WRDI 6.3 Read identification (RDID 6.4 Read status register (RDSR 6.4.1 2/47 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M45PE16 ...
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... M45PE16 6.4.2 6.5 Read data bytes (READ 6.6 Read data bytes at higher speed (FAST_READ 6.7 Page write (PW 6.8 Page program (PP 6.9 Page erase (PE 6.10 Sector erase (SE 6.11 Deep power-down (DP 6.12 Release from deep power-down (RDP Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 Maximum ratings ...
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... Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 16. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17. SO8W - 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4/47 M45PE16 ...
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... M45PE16 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. MLP and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20 Figure 9 ...
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... Description 1 Description The M45PE16 is a 16-Mbit (2 Mbit x8 bit) serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle ...
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... M45PE16 Figure 2. MLP and SO8 connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical M45PE16 Reset AI06885C section for package dimensions, and how to identify pin-1. ...
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... This input signal puts the device in the hardware protected mode, when Write Protect (W) is connected them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/47 , causing the first 256 pages of memory to become read-only by protecting M45PE16 ...
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... M45PE16 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal descriptions 9/47 ...
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... Resistors R (represented in that the M45PE16 is not selected if the bus master leaves the S line in the high impedance state. As the bus master may enter a state where all inputs/outputs are in high impedance at ...
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... M45PE16 Example pF, that is R*C p master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA µs <=> the application must ensure that the bus p MSB SPI modes MSB AI01438B 11/47 ...
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... For optimized timings recommended to use the page write (PW) instruction to write all consecutive targeted bytes in a single sequence versus using several page write (PW) sequences with each containing only a few bytes (see Table 12: AC characteristics - 50 MHz operation). 12/47 Section 6.7: Page write operation, and Table 13: AC characteristics - 75 MHz M45PE16 (PW), ...
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... M45PE16 4.3 A fast way to modify data The page program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had previously been set to ‘1’. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier page erase (PE) or sector erase (SE) instruction ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE16 boasts the following data protection mechanisms: Power-on reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M45PE16 5 Memory organization The memory is organized as: 8192 pages (256 bytes each). 2,097,152 bytes (8 bits each) 32 sectors (512 Kbits, 65536 bytes each) Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is page or sector erasable (bits are erased from 0 to 1). ...
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... High voltage generator I/O shift register 256-byte data buffer 010000h 000000h 256 bytes (page size) X decoder M45PE16 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh Status register 1FFFFFh First 256 pages can be made read-only 0000FFh ...
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... M45PE16 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (D), each bit being latched on the rising edges of Serial Clock (C) ...
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... The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 6. Write enable (WREN) instruction sequence 18/47 (Figure 6) sets the write enable latch (WEL) bit Instruction D High Impedance AI02281E M45PE16 ...
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... M45PE16 6.2 Write disable (WRDI) The write disable (WRDI) instruction The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is reset under the following conditions: ...
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... Table 4. Read identification (RDID) data-out sequence Manufacturer identification 20h Figure 8. Read identification (RDID) instruction sequence and data-out sequence 20/47 Figure 8. Device identification Memory type Memory capacity 40h 15h M45PE16 UID CFD length CFD content 10h 16 bytes ...
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... M45PE16 6.4 Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase or write cycle is in progress. When one of these cycles is in progress recommended to check the write in progress (WIP) bit before sending a new instruction to the device ...
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... Figure 10. Read data bytes (READ) instruction sequence and data-out sequence High Impedance Q 1. Address bits A23 to A21 are don’t care. 22/47 Figure 10 Instruction 24-bit address MSB Data out MSB M45PE16 Data out 2 7 AI03748D ...
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... M45PE16 6.6 Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... A page write (PW) instruction applied to a page that is hardware protected is not executed. Any page write (PW) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 24/47 Figure 12. Table 12: AC characteristics - 50 MHz operation). M45PE16 ...
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... M45PE16 Figure 12. Page write (PW) instruction sequence MSB 1. Address bits A23 to A21 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB Data byte 2 Data byte MSB Data byte MSB Data byte MSB Instructions AI04045 25/47 ...
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... A page program (PP) instruction applied to a page that is hardware protected is not executed. Any page program (PP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 26/47 Figure 13. and Table 13: AC characteristics - 75 MHz M45PE16 Table 12: AC operation). ...
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... M45PE16 Figure 13. Page program (PP) instruction sequence Data byte MSB 1. Address bits A23 to A21 are don’t care ≤ n ≤ 256 Instruction 24-bit address MSB Data byte MSB Instructions Data byte MSB Data byte MSB 0 AI04044 27/47 ...
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... Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Page erase (PE) instruction sequence Address bits A23 to A21 are don’t care. 28/47 Figure 14 Instruction 24-bit address 23 22 MSB M45PE16 ) is initiated AI04046 ...
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... M45PE16 6.10 Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch (WEL) ...
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... Any deep power-down (DP) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Deep power-down (DP) instruction sequence 30/47 Figure 16 Instruction M45PE16 specified in Table 11: CC1 CC2 before the supply current is reduced Standby mode Deep power-down mode AI03753D ...
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... M45PE16 6.12 Release from deep power-down (RDP) Once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (RDP) instruction. Executing this instruction takes the device out of the deep power-down mode. The release from deep power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on serial data input (D) ...
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... CC drops from the operating voltage, to below the POR threshold CC VSL modes. is less than the CC PUW threshold. However, the correct operation of is still below V (min). No write, program or CC (min), the device can be CC M45PE16 has elapsed feed. Each CC ...
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... M45PE16 Figure 18. Power-up timing (max (min) Reset state of the device V WI Table 6. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay before the first write, program or erase instruction PUW (1) V Write inhibit voltage WI 1. These parameters are characterized only, over the temperature range –40 °C to +85 °C. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ® ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). 34/47 Table 7: Absolute maximum ratings Parameter (2) M45PE16 may Min Max Unit –65 150 °C (1) See note ° ...
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... M45PE16 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... Input High voltage IH V Output Low voltage OL V Output High voltage OH 36/47 Test condition (in addition to Parameter those 0. 0. Min Table 0.9 MHz open / 0.9 MHz open – 0 –100 µA V –0.2 CC M45PE16 Max Unit ± 2 µA ± 2 µA 50 µA 10 µ ...
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... M45PE16 Table 12. AC characteristics - 50 MHz operation Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PW, PP, PE, SE, DP, RDP WREN, WRDI, RDSR, RDID f Clock frequency for read instructions R ( Clock High time CH CLH ( Clock Low time CL CLL Clock slew rate ...
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... A. For instance, int(12/ int(32/ int(15.3) =16. 38/47 (1) Table 8 Parameter (3) (peak to peak and Table 9 Min Typ Max D. 100 8 8 100 0.8 3 (6) int(n/8) × 0.025 Important note on M45PE16 Unit MHz MHz µs µ ...
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... M45PE16 Figure 20. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 21. Write protect setup and hold timing W tWHSL High Impedance Q Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tSLCH tCHSH tCHDX tCLCH MSB IN tCH tCLQV DC and AC parameters tSHSL tSHCH tCHCL LSB IN ...
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... Under completion of an erase or program cycle of a PW, PP, PE, SE operation Device deselected (S High) and in standby mode tSHRH tRLRH Table 8 and Table 9 Min Typ 10 10 (1) Table 8 and Table 9 Min Typ (2) : tRHSL M45PE16 Max Unit µs ns Max Unit 30 µs 300 µs 0 µs AI06808 ...
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... M45PE16 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... M45PE16 inches Typ Min Max 0.033 0.031 0.039 0.000 0.002 0.026 0.008 0.016 0.014 0.019 0.236 0.226 0.134 0.126 0.142 0.197 ...
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... M45PE16 Figure 25. SO8W - 8 lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 17. SO8W - 8 lead plastic small outline, 208 mils body width, package mechanical data Symbol (number of pins millimeters Typ Min Max 2.50 0.00 0.25 1.51 2.00 ...
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... Device tested with standard test flow Option blank = standard packing T = tape and reel packing Plating technology ECOPACK® (RoHS compliant) Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx sales office. 44/47 M45PE16 – M45PE16 T P ...
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... M45PE16 13 Revision history Table 19. Document revision history Date Version 30-Apr-2003 04-Jun-2003 26-Nov-2003 31-Mar-2004 23-Jul-2004 04-Aug-2005 15-Jun-2006 16-Oct-2006 09-Feb-2007 1.0 Initial release. Description corrected of entering hardware protected mode (W must be 1.1 driven, and cannot be left unconnected). V (min) extended to -0.6V, and t IO 2.0 t added. MLP8 and SO16 pages added, and LGA package SHWL removed ...
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... MHz) throughout the document. Added: Table 13: AC characteristics - 75 MHz operation 8 text in Section 11: Package Modified: Table 11: DC characteristics, devices on the SPI bus, Section 3: SPI identification (RDID). Changes and ECOPACK® mechanical. Figure 3: Bus master and memory modes, and Section 6.3: Read M45PE16 ...
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... M45PE16 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...