M28W640FST70ZA6 Micron Technology Inc, M28W640FST70ZA6 Datasheet - Page 14

• Manufacturer Part Number: M28W640FST70ZA6
• Manufacturer: Micron Technology Inc

Specifications of M28W640FST70ZA6

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Signal descriptions
2
2.1
2.2
2.3
2.4
2.5
2.6
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Signal descriptions
See
Signal
Address Inputs
The Address Inputs select the cells in the memory array to access during Bus Read
operations. Address Inputs range from A0 to A20 for the M28W320FS and M28W320FSU.
The M28W640FS and M28W640FSU have an additional A21 address line. During Bus
Write operations they control the commands sent to the Command Interface of the internal
state machine.
Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Write Bus operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V
mode. When Chip Enable is at V
impedance and the power consumption is reduced to the stand-by level.
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first.
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
minimized. After Reset all blocks are in the Locked state only if the volatile protection is
activated. When Reset is at V
device enters read array mode, but a negative transition of Chip Enable or a change of the
address is required to ensure valid data outputs.
Figure
names, for a brief overview of the signals connected to this devices.
1,
Figure
2,
Figure
IH
3, and
, the device is in normal operation. Exiting reset mode the
IH
the memory is deselected, the outputs are high
Figure
IL
4, Logic Diagrams in conjunction with
and Reset is at V
M28WxxxFS, M28WxxxFSU
IH
the device is in active
IL
, the
Table 2: