SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 13

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

3.2.3
3.2.3.1 Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]
Each endpoint set has a control register defined as follows:
Table 3-22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h]
3.2.3.2 Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]]
Pointer to memory buffer location for USB reads and writes.
Table 3-23. Endpoint Base Address Reg [Address; EP0a/b:01h/09h, EP1a/b:11h/19h, EP2a/b:21h/29h, EP3a/b:31h/39h]
3.2.3.3 Endpoint Base Length [Address a = (EP# * 10h)+2, b = (EP# * 10h)+A]
The Endpoint Base Length is the maximum packet size for IN/OUT transfers with the Host. Essentially, this designates the largest
packet size that can be received by the SL811HS with an OUT transfer, or it designates the size of the data packet to be sent to
the host for IN transfers.
Table 3-24. Endpoint Base Length Reg [Address EP0a/b:02h/0Ah, EP1a/b:12h/1Ah, EP2a/b:22h/2Ah, EP3a/b:32h/3Ah]
3.2.3.4 Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]
The packet status contains information relative to the packet that has been received or transmitted. The register is defined as
follows:
Table 3-25. Endpoint Packet Status Reg [Address EP0a/b:03h/0Bh, EP1a/b:13h/1Bh, EP2a/b:23h/2Bh, EP3a/b:33h/3Bh]
Document 38-08008 Rev. *B
Bit Position Bit Name
Bit Position Bit Name
EPxADD7
Reserved
EPxLEN7
Reserved
7
6
5
4
3
2
1
0
7
6
5
4
7
7
7
7
Endpoint Control Registers
Reserved
Sequence
Send STALL
ISO
Next Data Set
Direction
Enable
Arm
Reserved
Reserved
Overflow
Setup
Sequence
EPxADD6
EPxLEN6
Reserved
6
6
6
6
Send STALL
EPxADD5
EPxLEN5
Overflow
Function
Sequence Bit. '0' if DATA0, '1' if DATA1.
When set to ‘1’ sends Stall in response to next request on this endpoint.
When set to '1' allows Isochronous mode for this endpoint.
'0' if next data set is ‘a’, '1' if next data set is 'b'.
When Direction = '1' transmit to Host (IN). When Direction = '0', receive from Host (OUT).
When Enable = '1' allows transfers for this endpoint. When set 0 USB transactions are
ignored. If Enable = '1' and Arm = '0', the endpoint will return NAKs to USB transmissions.
Allows enabled transfers when set =’1’. Clears to '0' when transfer is complete.
Function
NA
NA
Overflow condition - maximum length exceeded during receives. This is considered a
serious error. The maximum number of bytes that can be received by an endpoint is deter-
mined by the Endpoint Base Length register for each endpoint. The Overflow bit is only
relevant during OUT Tokens from the host.
'1' indicates Setup Packet. If this bit is set, the last packet received was a setup packet.
5
5
5
5
EPxADD4
EPxLEN4
Setup
ISO
4
4
4
4
Next Data Set
EPxADD3
Sequence
EPxLEN3
3
3
3
3
EPxADD2
EPxLEN2
Direction
Time-out
2
2
2
2
EPxADD1
EPxLEN1
Enable
Error
1
1
1
1
SL811HS
Page 13 of 32
EPxADD0
EPxLEN0
ACK
Arm
0
0
0
0
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