SL811HST Cypress Semiconductor Corp, SL811HST Datasheet - Page 17

• Manufacturer Part Number: SL811HST
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

3.2.4.7 SOF Low Register, Address [15h]
Read only Register contains the 7 low order bits of Frame
Number in positions: bit 7:1. Bit 0 is undefined. Register is
updated when a SOF packet is received. User should not write
to this register.
3.2.4.8 SOF High Register, Address [16h]
Read only Register contains the 4 low order bits of Frame
Number in positions: bit 7:4. Bits 3:0 are undefined, and should
be masked when read by the user. This register is updated
when a SOF packet is received. The user should not write to
this register.
Document 38-08008 Rev. *B
Bit Position
5-0
6
Bit Name
SL811HS D+/D–
Data Polarity Swap
Reserved
Function
“1” = change polarity (low-speed)
“0” = no change of polarity (full-speed)
NA
3.2.4.9 DMA Total Count Low Register, Address [35h]
The DMA Total Count Low Register contains the low order 8-
bits of DMA count. DMA total count is the total number of bytes
to be transferred between a peripheral to the SL811HS. The
count may sometimes require up to 16-bits, thus the count is
represented in two registers: Total Count Low, and Total Count
High. EP3 is only supported with DMA operation.
3.2.4.10 DMA Total Count High Register, Address [36h]
The DMA Total Count High Register contains the High order
8-bits of DMA count. When written, this register enables DMA
if the DMA Enable bit is set in the Control Register 1. The user
should always write Low Count Register first, followed by a
write to High Count Register, even if high count is 00h.
SL811HS
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