M29W320ET70N6 Micron Technology Inc, M29W320ET70N6 Datasheet - Page 15

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M29W320ET70N6

Manufacturer Part Number
M29W320ET70N6
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of M29W320ET70N6

Cell Type
NOR
Density
32Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Top
Address Bus
22/21Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6/12V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
4M/2M
Supply Current
10mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

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0
2.7
2.8
2.9
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command interface.
V
The V
use an external high voltage power supply to reduce the time required for Program
operations. This is achieved by bypassing the unlock cycles and/or using the Double word
or Quadruple byte Program commands.
The Write Protect function provides a hardware method of protecting the two outermost boot
blocks. When V
blocks; Program and Erase operations in these blocks are ignored while V
is Low, even when RP is at V
When V
of the two outermost boot blocks. Program and Erase operations can now modify the data
in these blocks unless the blocks are protected using Block Protection.
When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I
programming circuits. See the description of the Unlock Bypass command in the Command
interface section. The transitions from V
t
Never raise V
memory may be left in an indeterminate state.
The V
become unreliable. A 0.1μF capacitor should be connected between the V
pin and the V
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
I
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if V
if RP is at V
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section,
Unprotect ac
Holding RP at V
and Erase operations on all blocks will be possible. The transition from V
slower than t
VHVPP
PP
PP/
.
PP
PP
PLPX
Write Protect (V
, see
PP
PP
/Write Protect pin provides two functions. The V
/Write Protect pin must not be left floating or unconnected or the device may
/Write Protect is High, V
/Write Protect is raised to V
. After Reset/Block Temporary Unprotect goes High, V
ID
Figure 17
PHPHH
PP
SS
waveforms, for more details.
PP
.
/WP is at V
PP
ID
/Write Protect to V
Ground pin to decouple the current surges from the power supply. The PCB
/Write Protect is Low, V
will temporarily unprotect the protected Blocks in the memory. Program
.
PP
/Write Protect returns to V
IL
, then the two outermost boot blocks will remain protected even
ID
PP
.
/WP)
PP
IH
, the memory reverts to the previous protection status
Table 16
from any mode except Read mode, otherwise the
PP
IH
the memory automatically enters the Unlock
IL
to V
, the memory protects the two outermost boot
and
PP
and from V
Figure 16: Reset/Block Temporary
IH
PHEL
or V
PP
or t
IL
function allows the memory to
normal operation resumes.
PP
RHEL
PP
to V
IH
, whichever occurs last.
from the pin to supply the
, the memory will be
IH
must be slower than
IH
PP
PP
to V
/Write Protect
/Write Protect
ID
must be
IL
, for at
15/65

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