LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 17

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

permanent lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set permanent lock-bit confirm (and any
device address). The WSM then controls the set lock-bit
algorithm. After
automatically outputs status register data when read (see
Figure IO). The CPU can detect the completion of the set
lock-bit event by analyzing the RY/BY#
status register bit SR.7.
When the set lock-bit operation is complete, status register
bit SR.4 should be checked. If an error is detected, the
status register should be cleared. The CUI will remain in
read status register mode until a new command is issued.
This two-step sequence of set-up followed by execution
ensures that lock-bits are not accidentally set. An invalid
Set Block or Permanent Lock-Bit
status register bits SR.4 and SR.5 being set to “1”. Also,
reliable operations occur only when V,,=2.7V-3.6V
V
lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the
permanent lock-bit be cleared. If it is attempted with the
permanent lock-bit set, SR.l and SR.4 will be set to “1”
and the operation will fail.
4.10 Set Block and Permanent Lock-Bit
A flexible block locking and unlocking scheme is enabled
via a combination of block lock-bits, a permanent lock-bit
and WP# pin. The block lock-bits
program and erase operations while the permanent lock-bit
gates block-lock
lock-bit not set, individual block lock-bits can be set using
the Set Block Lock-Bit
Lock-Bit command, sets the permanent lock-bit. After the
permanent lock-bit is set, block lock-bits and locked block
contents cannot altered. See Table 5 for a summary of
hardware and software write protection options.
Set block lock-bit and permanent lock-bit are executed by
a two-cycle
CCW=vCCWHl
SHARP
Commands
command sequence. The set block
l2. In the absence of this high voltage,
bit modification. With the permanent
the sequence is written,
command. The Set Permanent
command will result in
and WP# pin gates
pin output or
the device
and
or
LHFl6507
required to initialize block lock-bit
lock-bits operation requires that the permanent lock-bit is
not set. If it is attempted with the permanent lock-bit set,
fail.
If a clear block lock-bits operation is aborted due to V,,,
or V,,
transition,
undetermined state. A repeat of clear block lock-bits is
values. Once the permanent lock-bit is set, it cannot be
cleared.
This two-step sequence of set-up followed by execution
ensures that block lock-bits are not accidentally cleared.
An invalid Clear Block Lock-Bits command sequence will
result in status register bits SR.4 and SR.5 being set to “1”.
Also, a reliable clear block lock-bits operation can only
occur when V,,=2.7V-3.6V
clear block
vCCW’ v CCWLK,
absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block
SR.l and SR.5 will be set to “1” and the operation will
will remain in read status register mode until another
command is issued.
Clear block lock-bits operation is executed by a two-cycle
command sequence. A clear block lock-bits setup is first
written.
automatically outputs status register data when read (see
Figure 11). The CPU can detect completion of the clear
block lock-bits event by analyzing the RY/BY# Pin output
or status register bit SR.7.
When the operation is complete, status register bit SR.5
should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
4.11 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Cleai
Block Lock-Bits
not set, block lock-bits can be cleared using only the Clear
Block Lock-Bits
set, block lock-bits
summary of hardware
options.
transitioning out of valid range or RP# active
After
block
lock-bits
the command is written,
SR.3 and SR.5 will be set to “1”. In the
command. With the permanent lock-bit
command. If the permanent lock-bit is
lock-bit
cannot cleared. See Table 5 for a
operation
and software
and VCCW=VCCWHln.
values
is attempted while
contents to known
are
write
left
the device
protection
Rev. 1.2
in
If a
an
15