LH28F160BJHE-BTL70 Sharp Electronics, LH28F160BJHE-BTL70 Datasheet - Page 19

• Manufacturer Part Number: LH28F160BJHE-BTL70
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJHE-BTL70

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

SR.7 = WRITE STATE MACHINE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
SR.4 = WORD/BYTE
SR.3 = V,,,
SR.2 = WORD/BYTE
SR. 1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
SHARI=
WSMS
0 = Block Erase in Progress/Completed
0 = Successful Block Erase, Full Chip Erase or Clear
0 = Successful Word/Byte Write or Set Block/Permanent
0 = V,,,
0 = Word/Byte Write in Progress/Completed
0 = Unlock
0 = Busy
1 = Ready
1 = Block Erase Suspended
1 = Error in Block Erase, Full Chip Erase or Clear Block
1 = Error in Word/Byte Write or Set Block/Permanent
1 = Vccw Low Detect, Operation Abort
1 = Word/Byte Write Suspended
1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#
7
Lock-Bits
Block Lock-Bits
Lock-Bit
Lock-Bit
Lock Detected, Operation Abort
STATUS (ECBLBS)
STATUS (WBWSLBS)
(WBWSS)
OK
STATUS (VCCWS)
1
BESS
6
WRITE AND SET LOCK-BIT
WRITE SUSPEND STATUS
( ECBLBS
STATUS (WSMS)
5
‘Table 6. Status Register Definition
1 WBWSLBS
4
LHFl6507
(R)
1 VCCWS
erase or lock-bit configuration attempt, an improper
level. The WSM interrogates and indicates the Vccw level
only after Block Erase, Full Chip Erase, Word/Byte Write or
Lock-Bit Configuration command sequences. SR.3 is not
guaranteed to reports accurate feedback only when
vCCW+vCCWHl / 2.
SR. 1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
set, permanent lock-bit is set and/or WP# is V,,. Reading
the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Check RY/BY# or SR.7 to determine block erase, full chip
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7=“0”.
If both SR.5 and SR.4 are “1”s after a block erase, full chip
command sequence was entered.
SR.3 does not provide a continuous indication of Vccw
3
1 WBWSS
2
NOTES:
1
DPS
1
R
0
Rev. 1.: 1
17