LH28F016SCR-L95 Sharp Electronics, LH28F016SCR-L95 Datasheet - Page 9

• Manufacturer Part Number: LH28F016SCR-L95
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCR-L95

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

DQ
Symbol
RY/BY#
A
WE#
GND
CE#
RP#
OE#
V
0
V
NC
0
-A
CC
-DQ
PP
20
7
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
Type
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins float
to high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode. RP# at V
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP#=V
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with V
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY: For
erasing array blocks, writing bytes, or configuring lock-bits. With V
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V
attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V
operation. To switch from one voltage to another, ramp V
V
to the flash memory are inhibited. Device operations at invalid V
Characteristics) produce spurious results and should not be attempted. Block erase, byte
write and lock-bit configuration operations with V
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
CC
to the new voltage. Do not float any power pins. With V
IH
<RP#<V
PP
HH
(see DC Characteristics) produce spurious results and should not be
overrides block lock-bits thereby enabling block erase and byte write
HH
Table 2. Pin Descriptions
produce spurious results and should not be attempted.
LHF16CZN
Name and Function
CC
<3.0V are not supported.
CC
HH
CC
down to GND and then ramp
enables setting of the
≤V
CC
LKO
PP
voltage (see DC
≤V
, all write attempts
PPLK
, memory
Rev. 1.2
6