LH28F016LLT-12 Sharp Electronics, LH28F016LLT-12 Datasheet - Page 15

• Manufacturer Part Number: LH28F016LLT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F016LLT-12

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

16M (1M × 16, 2M × 8) Flash Memory
Timing Nomenclature
All 3.3 V system timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC
cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below:
t
t
t
t
t
CE
OE
ACC
AS
DH
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
3.0
0.0
3 V
W
Q
G
A
D
E
P
R
V
INPUT
t
t
t
t
t
ELQV
GLQV
AVQV
AVWH
WHDX
Reference Waveform (V
Address Inputs
Data Inputs
Data Outputs
CE
OE
WE (Write Enable)
RP
RY
Any Voltage Level
V
Figure 6. Transient Input/Output
CC
1.5
»
»
»
/ BY
»
(Chip Enable)
(Deep Power-Down Pin)
(Output Enable)
at 3.0 V Min.
PIN CHARACTERS
time (t) from CE
time (t) from OE
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
time (t) from address (A) valid (V) to WE
time (t) from WE
»
(Ready/Busy)
TEST POINTS
»
»
»
(E) going low (L) to the outputs (Q) becoming valid (V)
(G) going low (L) to the outputs (Q) becoming valid (V)
(W) going high (H) to when the data (D) can become undefined (X)
CC
= 3.3 V)
H
V
X
L
Z
1.5
OUTPUT
28F016LLT-6
High
Low
Valid
Driven, but not necessarily valid
High Impedance
»
(W) going high (H)
PIN STATES
FROM OUTPUT
UNDER TEST
Figure 7. Transient Equivalent Testing
Load Circuit (V
2.5 ns OF 50
TOTAL CAPACITANCE = 50 pF
CC
TRANSMISSION LINE
= 3.3 V)
LH28F016LL
28F016LLT-7
POINT
TEST
15