LH28F016LLT-12 Sharp Electronics, LH28F016LLT-12 Datasheet - Page 3

• Manufacturer Part Number: LH28F016LLT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F016LLT-12

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

16M (1M × 16, 2M × 8) Flash Memory
PIN DESCRIPTION
DQ
CE
DQ
SYMBOL
A
A
RY
16
1
8
»
0
0
WE
RP
OE
, CE
A
- A
- DQ
- A
- DQ
»
/ BY
0
»
»
15
20
»
1
»
15
7
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
TYPE
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A
input buffer is turned off when BYTE is high).
WORD-SELECT ADDRESSES: Select a word within one 64K block. A
1 of 1024 rows, and A
latched during Data Writes.
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS : Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS : Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE
specifications are the same for both signals. Device Selection
falling edge of CE
RESET/POWER-DOWN: RP
circuits that burn static power, even those circuits enabled in standby mode, are turned
off. When returning from Deep Power-Down, a recovery time of 5 ns is required to
allow these circuits to power-up for Read mode, and another 395 ns is required to enter
Program or Erase mode. When RP
are terminated, and the device is reset. All Status registers return to ready (with all
status flags cleared).
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
NOTE: CE
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE
Pin Disable command is issued.
»
X
overrides OE
»
0
or CE
1
- A
»
1
»
, and OE
. The first rising edge of CE
5
»
selects 16 of 512 columns. These addresses are
low places the device in a Deep Power-Down state. All
»
0
, CE
NAME AND FUNCTION
»
0
»
or CE
goes low, any current or pending WSM operation(s)
»
»
1
overrides WE.
»
is high.
must be low to select the device. All timing
»
»
1
or CE
»
/ BY
high, the device is de-selected and power
»
high indicates that the WSM is ready
»
0
, CE
»
1
»
0
are high), except if a RY
or CE
»
1
occ
disables the device.
urs with the latter
6
-
LH28F016LL
A
15
selects
»
/ BY
0
»
3