LH28F320BFHE-PBTLZ2 Sharp Electronics, LH28F320BFHE-PBTLZ2 Datasheet
LH28F320BFHE-PBTLZ2
Specifications of LH28F320BFHE-PBTLZ2
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LH28F320BFHE-PBTLZ2 Summary of contents
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... P P RELIMINARY RODUCT LH28F320BFHE-PBTLZ2 S PECIFICATIONS ® Flash Memory 32M (2M × 16) (Model No.: LHF32FD2) Issue Date: January 31, 2003 Integrated Circuits Group ...
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... Flash Memory LH28F320BFHE-PBTLZ2 Date Jan. 31. 2003 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, ...
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TSOP Pinout................................................. 3 Pin Descriptions.......................................................... 4 Simultaneous Operation Modes Allowed with Four Planes .................................. 5 Memory Map .............................................................. 6 Identifier Codes and OTP Address for Read Operation ............................................. 7 Identifier Codes and OTP Address for Read Operation on Partition ...
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... LH28F320BFHE-PBTLZ2 Page Mode Dual Work Flash MEMORY 32M density with 16Bit I/O Interface High Performance Reads • 80/35ns 8-Word Page Mode Configurative 4-Plane Dual Work • Flexible Partitioning • Read operations during Block Erase or (Page Buffer) Program • Status Register for Each Partition Low Power Operation • ...
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WE# 11 RST WP ...
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... Use of this pin at 12V beyond these limits may reduce block cycling capability or cause permanent damage. DEVICE POWER SUPPLY (2.7V-3.6V): With V V SUPPLY flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output V ...
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Table 2. Simultaneous Operation Modes Allowed with Four Planes THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE Read Read Read PARTITION IS: Array ID/OTP Status Read Array Read ID/OTP Read Status ...
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LHF32FD2 BLOCK NUMBER ADDRESS RANGE 70 32K-WORD 1F8000H - 1FFFFFH 69 32K-WORD 1F0000H - 1F7FFFH 68 32K-WORD 1E8000H - 1EFFFFH 67 32K-WORD 1E0000H - 1E7FFFH 66 32K-WORD 1D8000H - 1DFFFFH 65 32K-WORD 1D0000H - 1D7FFFH 64 32K-WORD 1C8000H - 1CFFFFH ...
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Table 3. Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code Bottom Parameter Device Code Block Lock Configuration Block is Unlocked Code Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code ...
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LHF32FD2 [ 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H Reserved for Future Implementation 000080H (DQ - Customer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ Figure 3. OTP ...
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Table 5. Bus Operation Mode Notes RST# CE# Read Array Output Disable Standby Reset Read Identifier Codes/OTP V ...
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... OTP block (See Table 3 and Table 4). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST ...
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LH28F320BF series for details the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be ...
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Table 7. Functions of Block Lock Current State (1) (1) State WP [000 ( [001] [011 [100 ( [101 ...
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Table 9. Block Locking State Transitions upon WP# Transition Current State Previous State State WP# - [000 [001] 0 (2) [110] [011] 0 (2) Other than [110] - [100 [101 [110 [111] ...
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WSMS BESS BEFCES SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS ...
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Table 11. Extended Status Register Definition SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page ...
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Table 12. Partition Configuration Register Definition PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 ...
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Electrical Specifications * 1.1 Absolute Maximum Ratings Operating Temperature During Read, Erase and Program ...-40°C to +85°C Storage Temperature During under Bias............................... -40°C to +85°C During non Bias................................ -65°C to +125°C Voltage On Any Pin (except V and V ...
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Capacitance (T =+25°C, f=1MHz) A Parameter Symbol Input Capacitance C IN Output Capacitance C OUT NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions V CCQ INPUT V 0.0 AC test inputs are driven at V ...
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DC Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Automatic Power Savings Current CCAS Reset Power-Down Current CCD CC Average V Read CC ...
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Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Normal PP V PPLK Operations V during Block Erase, Full Chip PP V Erase, (Page ...
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AC Characteristics - Read-Only Operations Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t Page Address Access Time APA t OE# to Output Delay GLQV t RST# High to ...
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(A) 20 EHEL V IH CE# ( AVEL t AVGL t GHGL V IH OE# ( (W) WE High (D/Q) 15-0 ...
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(A) 20 (A) 2 CE# ( OE# ( WE# ( High (D/Q) 15-0 V ...
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(A) 20 AVQV V IH VALID A (A) 2-0 ADDRESS CE# ( ELQV V IH OE# ( WE# ( GLQX ...
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AC Characteristics - Write Operations Symbol t Write Cycle Time AVAV RST# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL t (t ...
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NOTE 1 NOTE VALID A (A) 20-0 ADDRESS AVAV V IH CE# ( ELWL WLEL V IH OE# ( PHWL PHEL V IH WE# ...
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Reset Operations V IH RST# ( High (D/Q) 15 RST# ( High (D/Q) 15 (min GND V ...
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Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 ...
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Related Document Information Document No. FUM00701 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. LHF32FD2 (1) Document Name LH28F320BF series Appendix 29 Rev. 2.44 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol Parameter t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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A-3 STATUS REGISTER READ OPERATIONS If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the status register bit SR.15 instead of SR.7 to determine when the erase or program operation ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...