LH28F320S5HNS-ZP Sharp Electronics, LH28F320S5HNS-ZP Datasheet
LH28F320S5HNS-ZP
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LH28F320S5HNS-ZP Summary of contents
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... RELIMINARY RODUCT PECIFICATION LH28F320S5HNS-ZP Flash Memory 32Mbit (4Mbitx8/2Mbitx16) (Model Number: LHF32KZP) Spec. Issue Date: October 19, 2004 Lead-free (Pb-free) Spec No: EL16X167 Integrated Circuits Group ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION ...................................................... 3 1.1 Product Overview ................................................ 3 2 PRINCIPLES OF OPERATION ................................ 6 2.1 Data Protection ................................................... 6 3 BUS OPERATION.................................................... 8 3.1 Read ................................................................... 8 3.2 Output Disable .................................................... 8 3.3 Standby ............................................................... 8 3.4 Deep Power-Down ...
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... GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F320S5HNS-ZP is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F320S5HNS-ZP is manufactured on SHARP’ ...
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... Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Product Overview The LH28F320S5HNS- high-performance 32M-bit Smart 5 Flash memory organized as 4MBx8/2MBx16. The 4MB of data is arranged in sixty-four 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3 ...
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LHF32KZP DQ Output Buffer Comparator Y Input Decoder Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram ...
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... BYTE# V places the device in x16 mode , and turns off the A 8-15 IH ≤V , memory contents cannot be altered. Block PP PPLK ≤V , all write attempts to the flash memory are CC LKO voltage (see DC Characteristics) produce CC to select the devices RP# inhibits IL Locked blocks can not Rev ...
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... PRINCIPLES OF OPERATION The LH28F320S5HNS-ZP Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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Block 1F0000 1EFFFF 64K-byte Block 1E0000 1DFFFF 64K-byte Block 1D0000 1CFFFF 64K-byte Block 1C0000 1BFFFF 64K-byte Block 1B0000 1AFFFF 64K-byte Block 1A0000 19FFFF 64K-byte Block 190000 18FFFF 64K-byte Block 180000 17FFFF 64K-byte Block 170000 16FFFF 64K-byte Block 160000 ...
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... Time t goes to logic-high (V be written. As with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, full ), the device IH ...
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... Query Operation The query operation outputs the query structure. Query database is stored in the 48Byte ROM. Query structure allows system software to gain critical information for controlling the flash component. Query structure are always presented on the lowest- order data output (DQ 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes ...
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Mode Notes RP# Read 1,2,3,9 V Output Disable 3 V Standby 3 V Deep Power-Down 4 V Read Identifier 9 V Codes Query 9 V Write 3,7,8,9 V Mode Notes RP# Read 1,2,3,9 V Output Disable 3 V Standby 3 ...
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Command Read Array/Reset Read Identifier Codes Query Read Status Register Clear Status Register Block Erase Setup/Confirm Full Chip Erase Setup/Confirm Word/Byte Write Setup/Write Alternate Word/Byte Write Setup/Write Multi Word/Byte Write Setup/Confirm Block Erase and (Multi) Word/byte Write Suspend Confirm and ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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... Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component address is ignored when X8 mode (BYTE#=V Query data are always presented on the low-byte ...
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... CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) 10H,11H,12H 03H 13H,14H 02H 15H,16H ...
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... SCS OEM Specific Extended Query Table Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional vendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s). ...
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Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an address ...
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... XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F320S5HNS-ZP has two buffers error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. Status register bit SR.4 will be set to " ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS will return to V ...
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Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V individual block lock-bits can be set using the Set Block Lock-Bit command. See ...
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STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Suspend 0 SR.7= Word/Byte Yes Write 1 Full Status Check if Desired Word/byte Write Complete ...
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Start Write E8H, Start Address Read Extend Status Register No 0 Yes Write Buffer XSR.7= Time Out 1 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=0 Yes Abort Buffer Write Another Write Commnad? Block ...
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FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 SR.3= V Range Error SR.1= Device Protect Error 0 1 Command Sequence SR.4,5= Error 0 1 Multi Word/Byte Write SR.4= Error 0 Multi Word/Byte ...
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Start Write B0H Read Status Register 0 SR. Block Erase Completed SR.6= 1 (Multi) Word/Byte Write Read Read or Write ? Read Array Data (Multi) Word/Byte Write Loop No Done? Yes Write FFH Write D0H Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR. (Multi) Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Read Array Data Resumed Figure 11. (Multi) Word/Byte ...
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Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP 0 ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error SR.1= Device Protect ...
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... V GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5 Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V The V PP block erase, full chip erase, (multi) word/byte write ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility or CE# transitions increases usable battery life because data is retained when system power is removed. ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration .....-40°C to +85°C Temperature under Bias............... -40°C to +85°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except )............... ...
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AC INPUT/OUTPUT TEST CONDITIONS 3.0 INPUT 0.0 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% ...
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DC CHARACTERISTICS Symbol Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Write Current CCW CC ...
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Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal PPLK PP Operations V V during ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS V (4) Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/ PHQV V IH RP#( NOTE: ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...
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AC CHARACTERISTICS - WRITE OPERATIONS V (5) Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going PHWL Low t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# ...
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V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ High Z STS( WP#( ...
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ALTERNATIVE CE#-CONTROLLED WRITES V (5) Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup ...
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V IH ADDRESSES( WE#( OE#( CE#( High Z DATA(D/ High Z STS( WP#( ...
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RESET OPERATIONS High Z STS( RP#( High Z STS( RP#( RP#( Figure 21. AC Waveform for Reset Operation ...
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BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE V Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in ...
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... Product line designator for all SHARP Flash products Device Density 320 = 32-Mbit Architecture S = Regular Block Power Supply Type 5 = Smart 5 Technology Operating Temperature Blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1 LH28F320S5HNS-ZP LHF32KZP - Access Speed (ns) 90:90ns (5V,30pF), 100ns (5V) 12:120ns (5V) Package NS = 56-Lead SSOP B = 80-Ball CSP Valid Operational Combinations V =5V±0.5V ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...